void i2cEnableInterrupt (BOOL bIsEnableINT)
{ UINT32 regdata;
//k09144-1 sysSetInterruptType(IRQ_FI2C, LOW_LEVEL_SENSITIVE); //k08184-1
#ifdef ECOS
if (bIsEnableINT) // enable I2C interrupt
{ cyg_interrupt_create(IRQ_FI2C, 1, 0, Int_Handler_FastI2C, NULL,
&int_handle_I2C, &int_holder_I2C);
cyg_interrupt_attach(int_handle_I2C);
cyg_interrupt_unmask(IRQ_FI2C);
}
else
{ cyg_interrupt_mask(IRQ_FI2C);
cyg_interrupt_detach(int_handle_I2C);
}
#else
sysInstallISR(IRQ_LEVEL_1, IRQ_FI2C, (PVOID)Int_Handler_FastI2C); //IRQ_FI2C=24
if (bIsEnableINT) sysEnableInterrupt(IRQ_FI2C); //k03224-1
else sysDisableInterrupt (IRQ_FI2C);
#endif
_i2c_bINT_EN=bIsEnableINT; //k07195-1
//enable sensor I2C engine's interrupt
if (bIsEnableINT)
{ regdata=inpw (REG_FastSerialBusCR)|0x02;
outpw (REG_FastSerialBusCR,regdata);
}
//To clear interrupt status
regdata=inpw (REG_FastSerialBusStatus)|0x03;
outpw (REG_FastSerialBusStatus,regdata);
/* enable I2C interrupt */
//k08204-1 sysEnableInterrupt(IRQ_FI2C); //k03224-1
}
void capInit(BOOL bCapEngEnable, BOOL bCapIntEnable)
#endif
{
int j;
int i=sizeof(VCEInit)/sizeof(T_REG_INFO);
for (j=0; j<i ;j++)
outpw((CAP_BA+VCEInit[j].uAddr),VCEInit[j].uValue);
if(bCapEngEnable==TRUE)
{
outpw(REG_CAPEngine,inpw(REG_CAPEngine)|0x01);
}
else
{
outpw(REG_CAPEngine,inpw(REG_CAPEngine)&0xfffffffe);
}
if(bCapIntEnable==TRUE)
{
#ifdef ECOS
cyg_interrupt_disable();
cyg_interrupt_create(IRQ_VCE, 1, 0, capIntHandler, capIntHandlerDSR,
&(t_eCos->cap_int_handle), &(t_eCos->cap_int));
cyg_interrupt_attach(t_eCos->cap_int_handle);
cyg_interrupt_unmask(IRQ_VCE);
cyg_interrupt_enable();
#else
sysInstallISR(IRQ_LEVEL_1, IRQ_VCE, (PVOID)capIntHandler); //
sysEnableInterrupt(IRQ_VCE);
#endif
outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)|0x2);
}
else
{
#ifdef ECOS
cyg_interrupt_mask(IRQ_VCE);
cyg_interrupt_detach(t_eCos->cap_int_handle);
cyg_interrupt_delete(t_eCos->cap_int_handle);
#else
sysDisableInterrupt(IRQ_VCE);
#endif
outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)&0xfffffffd);
}
}
INT w5691StopPlay()
{
#ifdef SOFT_MODE
INT bytes;
#endif
const UINT8 abyCmdStopSpeech[] = { 0x03, 0x04, 0x02 };
#ifdef ECOS
cyg_interrupt_mask(GPIO_INT_NUM);
cyg_interrupt_detach(_tW5691.int_handle_play);
#else
sysDisableInterrupt(GPIO_INT_NUM);
#endif
#ifdef SOFT_MODE
//outpw(REG_ACTL_M80CON, 0x25202);
outpw(REG_ACTL_M80CON, inpw(REG_ACTL_M80CON) | W_GFIFO );
soft_write_command_byte_reg(0x08);
soft_write_data_reg(0x55);
for (bytes=0;bytes<3;bytes++){
soft_write_data_reg(abyCmdStopSpeech[bytes]);
}
//outpw(REG_ACTL_M80CON, 0x5202);
outpw(REG_ACTL_M80CON, inpw(REG_ACTL_M80CON) & ~W_GFIFO );
#else
outpw(REG_ACTL_M80SIZE, sizeof(abyCmdStopSpeech)+1);
outpw(REG_ACTL_M80DATA0, 0x55 | abyCmdStopSpeech[0]<<8 | (abyCmdStopSpeech[1]<<16) | (abyCmdStopSpeech[2]<<24) );
outpw(REG_ACTL_M80ADDR, 0x08);
//outpw(REG_ACTL_M80CON, 0x25210);
outpw(REG_ACTL_M80CON, inpw(REG_ACTL_M80CON) | W_GFIFO | W_IF12_ACT);
while((inpw(REG_ACTL_M80CON)&W_IF12_ACT) != 0);
//outpw(REG_ACTL_M80CON, 0x5200);
outpw(REG_ACTL_M80CON, inpw(REG_ACTL_M80CON) & ~W_GFIFO );
#endif
ComDrv_SendCommand(eCOMMAND_DISABLE_SPEECH_INTERRUPT);
DevDrv_PowerDown();
_W5691_Playing = 0;
return 0;
}
void kintr0_main( void )
{
cyg_vector_t v = (CYGNUM_HAL_VSR_MIN + 11) % CYGNUM_HAL_VSR_COUNT;
cyg_vector_t v1;
cyg_vector_t lvl1 = CYGNUM_HAL_ISR_MIN + (1 % CYGNUM_HAL_ISR_COUNT);
cyg_vector_t lvl2 = CYGNUM_HAL_ISR_MIN + (15 % CYGNUM_HAL_ISR_COUNT);
int in_use;
cyg_VSR_t *old_vsr, *new_vsr;
CYG_TEST_INIT();
#ifdef CYGPKG_HAL_MIPS_TX39
// This can be removed when PR 17831 is fixed
if ( cyg_test_is_simulator )
v1 = 12 % CYGNUM_HAL_ISR_COUNT;
else /* NOTE TRAILING ELSE... */
#endif
v1 = CYGNUM_HAL_ISR_MIN + ( 6 % CYGNUM_HAL_ISR_COUNT);
CHECK(flash());
CHECK(flash());
// Make sure the chosen levels are not already in use.
HAL_INTERRUPT_IN_USE( lvl1, in_use );
intr0 = 0;
if (!in_use)
cyg_interrupt_create(lvl1, PRIO_B, (cyg_addrword_t)777,
isr0, dsr0, &intr0, &intr_obj[0]);
HAL_INTERRUPT_IN_USE( lvl2, in_use );
intr1 = 0;
if (!in_use && lvl1 != lvl2)
cyg_interrupt_create(lvl2, PRIO_C, 888,
isr1, dsr1, &intr1, &intr_obj[1]);
// Check these functions at least exist
cyg_interrupt_disable();
cyg_interrupt_enable();
if (intr0)
cyg_interrupt_attach(intr0);
if (intr1)
cyg_interrupt_attach(intr1);
if (intr0)
cyg_interrupt_detach(intr0);
if (intr1)
cyg_interrupt_detach(intr1);
// If this attaching interrupt replaces the previous interrupt
// instead of adding to it we could be in a big mess if the
// vector is being used by something important.
cyg_interrupt_get_vsr( v, &old_vsr );
cyg_interrupt_set_vsr( v, vsr0 );
cyg_interrupt_get_vsr( v, &new_vsr );
CHECK( vsr0 == new_vsr );
new_vsr = NULL;
cyg_interrupt_get_vsr( v, &new_vsr );
cyg_interrupt_set_vsr( v, old_vsr );
CHECK( new_vsr == vsr0 );
cyg_interrupt_set_vsr( v, new_vsr );
new_vsr = NULL;
cyg_interrupt_get_vsr( v, &new_vsr );
CHECK( vsr0 == new_vsr );
cyg_interrupt_set_vsr( v, old_vsr );
CHECK( vsr0 == new_vsr );
new_vsr = NULL;
cyg_interrupt_get_vsr( v, &new_vsr );
CHECK( old_vsr == new_vsr );
CHECK( NULL != vsr0 );
cyg_interrupt_mask(v1);
cyg_interrupt_unmask(v1);
cyg_interrupt_configure(v1, true, true);
CYG_TEST_PASS_FINISH("Kernel C API Intr 0 OK");
}
