int tsif_set_pmt_config(struct inode *inode, unsigned long arg)
{
struct tsif_pmt_config pmt_cfg;
char *pmt_cfg_buff_ptr;
u32 inten;
struct tsif_control_dev *tsif_dev;
unsigned int index, minor = iminor(inode);
index = minor / tsif_control_minor_count;
tsif_dev = tsif_control_dev_get_by_major(index);
/* copy the parameters to the configuration */
if (copy_from_user(&pmt_cfg,
(struct tsif_pmt_config *)arg,
sizeof(struct tsif_pmt_config)))
return -EFAULT;
davinci_writel(TSIF_PMT_SENSE_CFG_RESETVAL,
tsif_dev->base + PMT_SENSE_CFG);
inten = davinci_readl(tsif_dev->base + INTEN);
inten &= ~TSIF_INTEN_PMT_DETECT_INTEN;
davinci_writel(inten, tsif_dev->base + INTEN);
pmt_cfg_buff_ptr = (char *)virt_to_phys(kmalloc(4096, GFP_KERNEL));
if (pmt_cfg_buff_ptr == NULL)
return -1;
davinci_writel((u32) pmt_cfg_buff_ptr, tsif_dev->base + PMT_STORE_ADD);
davinci_writel((TSIF_PMT_SENSE_CFG_PMT_SENSE_EN | (u32) pmt_cfg.
pmt_pid), tsif_dev->base + PMT_SENSE_CFG);
/* Clear PMT_detect */
davinci_writel(TSIF_INTEN_CLR_PMT_DETECT_INTEN_CLR,
tsif_dev->base + INT_STATUS_CLR);
/* PMT_detect_inten<-1 */
inten = davinci_readl(tsif_dev->base + INTEN);
inten |= TSIF_INTEN_SET_PMT_DETECT_INTEN_SET;
davinci_writel(inten, tsif_dev->base + INTEN);
/* PAT_detect_inten_set<-1 */
inten = davinci_readl(tsif_dev->base + INTEN_SET);
inten |= TSIF_INTEN_SET_PMT_DETECT_INTEN_SET;
davinci_writel(inten, tsif_dev->base + INTEN_SET);
init_completion(&tsif_isr_data.pmt_complete);
tsif_isr_data.pmt_complete.done = 0;
return 0;
}
int tsif_control_open(struct inode *inode, struct file *file)
{
unsigned int index, minor = iminor(inode);
struct tsif_control_dev *tsif_dev;
index = minor / tsif_control_minor_count;
tsif_dev = tsif_control_dev_get_by_major(index);
tsif_dev->tsif_clk = clk_get(NULL, *(tsif_clk_name + index));
if (IS_ERR(tsif_dev->tsif_clk)) {
printk(KERN_ERR "Cannot get TSIF clock\n");
return -1;
}
clk_enable(tsif_dev->tsif_clk);
tsif_int_status = 0;
davinci_writel(0x00000001, tsif_dev->base + EMULATION_CTRL);
/* Enable the interrupt to arm */
davinci_writel((davinci_readl(tsif_dev->base + CTRL1) | 0x8000),
tsif_dev->base + CTRL1);
return 0;
}
int tsif_set_pat_config(struct inode *inode, unsigned long arg)
{
char *pat_cfg_buff_ptr;
u32 inten;
struct tsif_control_dev *tsif_dev;
unsigned int index, minor = iminor(inode);
index = minor / tsif_control_minor_count;
tsif_dev = tsif_control_dev_get_by_major(index);
davinci_writel(TSIF_PAT_SENSE_CFG_RESETVAL,
tsif_dev->base + PAT_SENSE_CFG);
inten = davinci_readl(tsif_dev->base + INTEN);
inten &= ~TSIF_INTEN_PAT_DETECT_INTEN;
davinci_writel(inten, tsif_dev->base + INTEN);
pat_cfg_buff_ptr = (char *)virt_to_phys(kmalloc(192, GFP_KERNEL));
if (pat_cfg_buff_ptr == NULL)
return -1;
davinci_writel((u32) pat_cfg_buff_ptr, tsif_dev->base + PAT_STORE_ADD);
/* Clear PAT_detect */
davinci_writel(TSIF_INTEN_CLR_PAT_DETECT_INTEN_CLR,
tsif_dev->base + INT_STATUS_CLR);
davinci_writel(TSIF_PAT_SENSE_CFG_PAT_SENSE_EN,
tsif_dev->base + PAT_SENSE_CFG);
/* PAT_detect_inten<-1 */
inten = davinci_readl(tsif_dev->base + INTEN);
inten |= TSIF_INTEN_SET_PAT_DETECT_INTEN_SET;
davinci_writel(inten, tsif_dev->base + INTEN);
/* PAT_detect_inten_set<-1 */
inten = davinci_readl(tsif_dev->base + INTEN_SET);
inten |= TSIF_INTEN_SET_PAT_DETECT_INTEN_SET;
davinci_writel(inten, tsif_dev->base + INTEN_SET);
init_completion(&tsif_isr_data.pat_complete);
tsif_isr_data.pat_complete.done = 0;
return 0;
}
/*
* Sets the DAVINCI MUX register based on the table
*/
int __init_or_module davinci_cfg_reg(const unsigned long index)
{
static DEFINE_SPINLOCK(mux_spin_lock);
unsigned long flags;
struct pin_config *cfg;
unsigned int reg_orig = 0, reg = 0;
unsigned int mask, warn = 0;
if (!pin_table)
BUG();
if (index >= pin_table_sz) {
printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
index, pin_table_sz);
dump_stack();
return -ENODEV;
}
cfg = (struct pin_config *)&pin_table[index];
/* Check the mux register in question */
if (cfg->mux_reg) {
unsigned tmp1, tmp2;
spin_lock_irqsave(&mux_spin_lock, flags);
reg_orig = davinci_readl(cfg->mux_reg);
mask = (cfg->mask << cfg->mask_offset);
tmp1 = reg_orig & mask;
reg = reg_orig & ~mask;
tmp2 = (cfg->mode << cfg->mask_offset);
reg |= tmp2;
if (tmp1 != tmp2)
warn = 1;
davinci_writel(reg, cfg->mux_reg);
spin_unlock_irqrestore(&mux_spin_lock, flags);
}
if (warn) {
#ifdef CONFIG_DAVINCI_MUX_WARNINGS
printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
#endif
}
#ifdef CONFIG_DAVINCI_MUX_DEBUG
if (cfg->debug || warn) {
printk(KERN_WARNING "MUX: Setting register %s\n", cfg->name);
printk(KERN_WARNING " %s (0x%08x) = 0x%08x -> 0x%08x\n",
cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
}
#endif
return 0;
}
/* Enable or disable a PSC domain */
void davinci_psc_config(unsigned int domain, unsigned int id, char enable)
{
u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl, mdstat_mask;
if (id < 0)
return;
mdctl = davinci_readl(MDCTL + 4 * id);
if (enable)
mdctl |= 0x00000003; /* Enable Module */
else
mdctl &= 0xFFFFFFF2; /* Disable Module */
davinci_writel(mdctl, MDCTL + 4 * id);
pdstat = davinci_readl(PDSTAT);
if ((pdstat & 0x00000001) == 0) {
pdctl1 = davinci_readl(PDCTL1);
pdctl1 |= 0x1;
davinci_writel(pdctl1, PDCTL1);
ptcmd = 1 << domain;
davinci_writel(ptcmd, PTCMD);
do {
epcpr = davinci_readl(EPCPR);
} while ((((epcpr >> domain) & 1) == 0));
pdctl1 = davinci_readl(PDCTL1);
pdctl1 |= 0x100;
davinci_writel(pdctl1, PDCTL1);
do {
ptstat = davinci_readl(PTSTAT);
} while (!(((ptstat >> domain) & 1) == 0));
} else {
int __init da8xx_clk_init(void)
{
u32 pll_mult;
davinci_psc_register(da8xx_psc_bases, 2);
pll_mult = davinci_readl(DA8XX_PLL_CNTRL0_BASE + PLLM);
armrate = ((pll_mult + 1) * DA8XX_CLOCK_TICK_RATE) / 2;
commonrate = armrate / 2;
div_by_four = armrate / 4;
return davinci_enable_clks(da8xx_clks, ARRAY_SIZE(da8xx_clks));
}
static irqreturn_t imp_common_isr(int irq, void *device_id,
struct pt_regs *regs)
{
u32 val;
if (cpu_is_davinci_dm365()) {
val = davinci_readl(0x1c7000c);
if (val & 0x8000) {
davinci_writel(0x8000, 0x1c7000c);
complete(&(imp_serializer_info.sem_isr));
}
} else
complete(&(imp_serializer_info.sem_isr));
return IRQ_HANDLED;
}
int tsif_stop_rx(struct inode *inode)
{
unsigned int index, minor = iminor(inode);
struct tsif_control_dev *tsif_dev;
unsigned int ctrl0;
index = minor / tsif_control_minor_count;
tsif_dev = tsif_control_dev_get_by_major(index);
ctrl0 = davinci_readl(tsif_dev->base + CTRL0);
ctrl0 &= ~(TSIF_CTRL0_RCV_DMA_CTL | TSIF_CTRL0_RCV_CTL);
davinci_writel(ctrl0, tsif_dev->base + CTRL0);
tsif_rx_enable = 0;
return 0;
}
void davinci_mux_peripheral(unsigned int mux, unsigned int enable)
{
u32 pinmux, muxreg = PINMUX0_M;
if (mux >= DAVINCI_MUX_LEVEL2) {
muxreg = PINMUX1_M;
mux -= DAVINCI_MUX_LEVEL2;
}
pinmux = davinci_readl(DAVINCI_SYSTEM_MODULE_BASE + muxreg);
if (enable)
pinmux |= (1 << mux);
else
pinmux &= ~(1 << mux);
davinci_writel(pinmux, DAVINCI_SYSTEM_MODULE_BASE + muxreg);
}
/* reset board using watchdog timer */
void davinci_watchdog_reset(void) {
u32 tgcr, wdtcr, base = DAVINCI_WDOG_BASE;
/* disable, internal clock source */
davinci_writel(0, base + TCR);
/* reset timer, set mode to 64-bit watchdog, and unreset */
tgcr = 0;
davinci_writel(tgcr, base + TCR);
tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT;
tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
(TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
davinci_writel(tgcr, base + TCR);
/* clear counter and period regs */
davinci_writel(0, base + TIM12);
davinci_writel(0, base + TIM34);
davinci_writel(0, base + PRD12);
davinci_writel(0, base + PRD34);
/* enable */
wdtcr = davinci_readl(base + WDTCR);
wdtcr |= WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT;
davinci_writel(wdtcr, base + WDTCR);
/* put watchdog in pre-active state */
wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
davinci_writel(wdtcr, base + WDTCR);
/* put watchdog in active state */
wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) |
(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
davinci_writel(wdtcr, base + WDTCR);
/* write an invalid value to the WDKEY field to trigger
* a watchdog reset */
wdtcr = 0x00004000;
davinci_writel(wdtcr, base + WDTCR);
}
static int timer32_config(struct timer_s *t)
{
u32 tcr = davinci_readl(t->reg_base + TCR);
/* disable timer */
tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift);
davinci_writel(tcr, t->reg_base + TCR);
/* reset counter to zero, set new period */
davinci_writel(0, t->tim_reg);
davinci_writel(t->period, t->prd_reg);
/* Set enable mode */
if (t->opts & TIMER_OPTS_ONESHOT) {
tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift;
} else if (t->opts & TIMER_OPTS_PERIODIC) {
tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift;
}
davinci_writel(tcr, t->reg_base + TCR);
return 0;
}
int tsif_set_spec_pkt_config(struct inode *inode, unsigned long arg)
{
struct tsif_spcpkt_config spcpkt_cfg;
char *spcpkt_cfg_buff_ptr = NULL;
u32 inten, tsif_ctrl1;
struct tsif_control_dev *tsif_dev;
unsigned int index, minor = iminor(inode);
index = minor / tsif_control_minor_count;
tsif_dev = tsif_control_dev_get_by_major(index);
/* copy the parameters to the configuration */
if (copy_from_user(&spcpkt_cfg,
(struct tsif_spcpkt_config *)arg,
sizeof(struct tsif_spcpkt_config)))
return -EFAULT;
inten = davinci_readl(tsif_dev->base + INTEN);
inten &= ~TSIF_INTEN_SET_BOUNDARY_SPECIFIC_INTEN_SET;
davinci_writel(inten, tsif_dev->base + INTEN);
spcpkt_cfg_buff_ptr = (char *)virt_to_phys(kmalloc(4096, GFP_KERNEL));
if (spcpkt_cfg_buff_ptr == NULL)
return -1;
if (&spcpkt_cfg != NULL) {
if (spcpkt_cfg.pid < 0x2000) {
davinci_writel((u32) spcpkt_cfg.pid,
tsif_dev->base + BSP_PID);
tsif_ctrl1 = davinci_readl(tsif_dev->base + CTRL1);
tsif_ctrl1 |= TSIF_CTRL1_STREAM_BNDRY_CTL;
davinci_writel(tsif_ctrl1, tsif_dev->base + CTRL1);
} else {
tsif_ctrl1 = davinci_readl(tsif_dev->base + CTRL1);
tsif_ctrl1 &= ~TSIF_CTRL1_STREAM_BNDRY_CTL;
}
davinci_writel((u32) spcpkt_cfg_buff_ptr,
tsif_dev->base + BSP_STORE_ADD);
} else {
tsif_ctrl1 = davinci_readl(tsif_dev->base + CTRL1);
tsif_ctrl1 &= ~TSIF_CTRL1_STREAM_BNDRY_CTL;
davinci_writel(tsif_ctrl1, tsif_dev->base + CTRL1);
davinci_writel(TSIF_BSP_STORE_ADDR_RESETVAL,
tsif_dev->base + BSP_STORE_ADD);
}
/* Clear boundary_specific */
davinci_writel(TSIF_INTEN_CLR_BOUNDARY_SPECIFIC_INTEN_CLR,
tsif_dev->base + INT_STATUS_CLR);
/* boundary_specific_inten<-1 */
inten = davinci_readl(tsif_dev->base + INTEN);
inten |= TSIF_INTEN_SET_BOUNDARY_SPECIFIC_INTEN_SET;
davinci_writel(inten, tsif_dev->base + INTEN);
/* boundary_specific_inten_set<-1 */
inten = davinci_readl(tsif_dev->base + INTEN_SET);
inten |= TSIF_INTEN_SET_BOUNDARY_SPECIFIC_INTEN_SET;
davinci_writel(inten, tsif_dev->base + INTEN_SET);
init_completion(&tsif_isr_data.spcpkt_complete);
tsif_isr_data.spcpkt_complete.done = 0;
return 0;
}
static inline u32 timer32_read(struct timer_s *t)
{
return davinci_readl(t->tim_reg);
}
static inline unsigned int davinci_irq_readl(int offset)
{
return davinci_readl(DAVINCI_ARM_INTC_BASE + offset);
}
/* register access routines */
static inline u32 regr(u32 offset)
{
return davinci_readl(ccdc_base_addr + offset);
}
int tsif_control_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
unsigned long arg)
{
int ret = 0;
unsigned int index;
struct tsif_control_dev *tsif_dev;
index = iminor(inode) / tsif_control_minor_count;
tsif_dev = tsif_control_dev_get_by_major(index);
switch (cmd) {
case TSIF_SET_RX_CONFIG:{
tsif_set_rx_config(inode, arg);
break;
}
case TSIF_GET_RX_CONFIG:{
u32 tsif_ctrl0, tsif_ctrl1;
struct tsif_rx_config rx_cfg;
tsif_ctrl0 = davinci_readl(tsif_dev->base + CTRL0);
tsif_ctrl1 = davinci_readl(tsif_dev->base + CTRL1);
if ((tsif_ctrl0 & TSIF_CTRL0_RCV_IF_MODE_DMA) == 0) {
switch (tsif_ctrl0 &
TSIF_CTRL0_RCV_IF_MODE_MASK) {
case TSIF_CTRL0_RCV_IF_MODE_SER_SYN:
rx_cfg.if_mode = TSIF_IF_SERIAL_SYNC;
break;
case TSIF_CTRL0_RCV_IF_MODE_SER_ASYN:
rx_cfg.if_mode = TSIF_IF_SERIAL_ASYNC;
break;
case TSIF_CTRL0_RCV_IF_MODE_PAR_SYN:
rx_cfg.if_mode = TSIF_IF_PARALLEL_SYNC;
break;
case TSIF_CTRL0_RCV_IF_MODE_PAR_ASYN:
rx_cfg.if_mode = TSIF_IF_PARALLEL_ASYNC;
break;
}
} else
rx_cfg.if_mode = TSIF_IF_DMA;
if ((tsif_ctrl0 & TSIF_CTRL0_RCV_STREAM_MODE_TS_ACTIVE)
== 0)
rx_cfg.stream_mode = TSIF_STREAM_NON_TS;
else
rx_cfg.stream_mode = TSIF_STREAM_TS;
switch (tsif_ctrl0 & TSIF_CTRL0_RCV_ATS_MODE_MASK) {
case TSIF_CTRL0_RCV_ATS_MODE_IN_192:
rx_cfg.ats_mode = TSIF_RX_ATS_THROUGH;
break;
case TSIF_CTRL0_RCV_ATS_MODE_IN_188:
rx_cfg.ats_mode = TSIF_RX_ATS_NOADD;
break;
case TSIF_CTRL0_RCV_ATS_MODE_CHANGE_192:
rx_cfg.ats_mode = TSIF_RX_ATS_CHANGE;
break;
case TSIF_CTRL0_RCV_ATS_MODE_ADD_188:
rx_cfg.ats_mode = TSIF_RX_ATS_ADD;
break;
}
if ((tsif_ctrl1 & TSIF_CTRL1_PID_FILTER_EN_ACTIVATE) ==
0)
rx_cfg.filter_mode = TSIF_PID_FILTER_BYPASS;
else {
switch (tsif_ctrl1 &
TSIF_CTRL1_PID_FILTER_CTL_MASK) {
case TSIF_CTRL1_PID_FILTER_CTL_FULL_MAN:
rx_cfg.filter_mode =
TSIF_PID_FILTER_FULL_MANUAL;
break;
case TSIF_CTRL1_PID_FILTER_CTL_SEMI_A:
rx_cfg.filter_mode =
TSIF_PID_FILTER_SEMI_AUTO_A;
break;
case TSIF_CTRL1_PID_FILTER_CTL_SEMI_B:
rx_cfg.filter_mode =
TSIF_PID_FILTER_SEMI_AUTO_B;
break;
case TSIF_CTRL1_PID_FILTER_CTL_FULL_AUT:
rx_cfg.filter_mode =
TSIF_PID_FILTER_FULL_AUTO;
break;
default:
return -EINVAL;
}
}
if ((tsif_ctrl0 & TSIF_CTRL0_RCV_STREAM_MODE_TS_ACTIVE)
== 0) {
switch (tsif_ctrl0 &
TSIF_CTRL0_RCV_PKT_SIZE_MASK) {
case TSIF_CTRL0_RCV_PKT_SIZE_BYTE_200:
rx_cfg.pkt_size =
TSIF_200_BYTES_PER_PKT;
break;
case TSIF_CTRL0_RCV_PKT_SIZE_BYTE_208:
rx_cfg.pkt_size =
TSIF_208_BYTES_PER_PKT;
break;
case TSIF_CTRL0_RCV_PKT_SIZE_BYTE_216:
rx_cfg.pkt_size =
TSIF_216_BYTES_PER_PKT;
break;
case TSIF_CTRL0_RCV_PKT_SIZE_BYTE_224:
rx_cfg.pkt_size =
TSIF_224_BYTES_PER_PKT;
break;
case TSIF_CTRL0_RCV_PKT_SIZE_BYTE_232:
rx_cfg.pkt_size =
TSIF_232_BYTES_PER_PKT;
break;
case TSIF_CTRL0_RCV_PKT_SIZE_BYTE_240:
rx_cfg.pkt_size =
TSIF_240_BYTES_PER_PKT;
break;
case TSIF_CTRL0_RCV_PKT_SIZE_BYTE_248:
rx_cfg.pkt_size =
TSIF_248_BYTES_PER_PKT;
break;
case TSIF_CTRL0_RCV_PKT_SIZE_BYTE_256:
rx_cfg.pkt_size =
TSIF_256_BYTES_PER_PKT;
break;
default:
return -EINVAL;
}
} else
rx_cfg.pkt_size = 192;
/* copy the configuration to the user space */
if (copy_to_user((struct tsif_rx_config *)arg,
&rx_cfg,
sizeof(struct tsif_rx_config)))
return -EFAULT;
break;
}
case TSIF_SET_TX_CONFIG:{
tsif_set_tx_config(inode, arg);
break;
}
case TSIF_GET_TX_CONFIG:{
u32 tsif_ctrl;
struct tsif_tx_config tx_cfg;
tsif_ctrl = davinci_readl(tsif_dev->base + CTRL0);
switch (tsif_ctrl & TSIF_CTRL0_TX_IF_MODE) {
case TSIF_CTRL0_TX_IF_MODE_SER_SYN:
tx_cfg.if_mode = TSIF_IF_SERIAL_SYNC;
break;
case TSIF_CTRL0_TX_IF_MODE_SER_ASYN:
tx_cfg.if_mode = TSIF_IF_SERIAL_ASYNC;
break;
case TSIF_CTRL0_TX_IF_MODE_PAR_SYN:
tx_cfg.if_mode = TSIF_IF_PARALLEL_SYNC;
break;
case TSIF_CTRL0_TX_IF_MODE_PAR_ASYN:
tx_cfg.if_mode = TSIF_IF_PARALLEL_ASYNC;
break;
}
if ((tsif_ctrl & TSIF_CTRL0_TX_STREAM_MODE) == 0)
tx_cfg.stream_mode = TSIF_STREAM_NON_TS;
else
tx_cfg.stream_mode = TSIF_STREAM_TS;
switch (tsif_ctrl & TSIF_CTRL0_TX_ATS_MODE) {
case TSIF_CTRL0_TX_ATS_MODE_OUT_188:
tx_cfg.ats_mode = TSIF_TX_ATS_REMOVE;
break;
case TSIF_CTRL0_TX_ATS_MODE_OUT_192:
tx_cfg.ats_mode = TSIF_TX_ATS_THROUGH;
break;
}
tx_cfg.interval_wait =
davinci_readb(tsif_dev->base + ASYNC_TX_WAIT);
if ((tsif_ctrl & TSIF_CTRL0_TX_STREAM_MODE) == 0) {
switch (tsif_ctrl & TSIF_CTRL0_TX_PKT_SIZE) {
case TSIF_CTRL0_TX_PKT_SIZE_BYTE_200:
tx_cfg.pkt_size =
TSIF_200_BYTES_PER_PKT;
break;
case TSIF_CTRL0_TX_PKT_SIZE_BYTE_208:
tx_cfg.pkt_size =
TSIF_208_BYTES_PER_PKT;
break;
case TSIF_CTRL0_TX_PKT_SIZE_BYTE_216:
tx_cfg.pkt_size =
TSIF_216_BYTES_PER_PKT;
break;
case TSIF_CTRL0_TX_PKT_SIZE_BYTE_224:
tx_cfg.pkt_size =
TSIF_224_BYTES_PER_PKT;
break;
case TSIF_CTRL0_TX_PKT_SIZE_BYTE_232:
tx_cfg.pkt_size =
TSIF_232_BYTES_PER_PKT;
break;
case TSIF_CTRL0_TX_PKT_SIZE_BYTE_240:
tx_cfg.pkt_size =
TSIF_240_BYTES_PER_PKT;
break;
case TSIF_CTRL0_TX_PKT_SIZE_BYTE_248:
tx_cfg.pkt_size =
TSIF_248_BYTES_PER_PKT;
break;
case TSIF_CTRL0_TX_PKT_SIZE_BYTE_256:
tx_cfg.pkt_size =
TSIF_256_BYTES_PER_PKT;
break;
default:
return -EINVAL;
}
} else
tx_cfg.pkt_size = 192;
/* copy the configuration to the user space */
if (copy_to_user((struct tsif_tx_config *)arg,
&tx_cfg,
sizeof(struct tsif_tx_config)))
return -EFAULT;
break;
}
case TSIF_START_RX:{
u32 tsif_ctrl0;
tsif_ctrl0 = davinci_readl(tsif_dev->base + CTRL0);
tsif_ctrl0 |=
(TSIF_CTRL0_RCV_DMA_CTL | TSIF_CTRL0_RCV_CTL);
davinci_writel(tsif_ctrl0, tsif_dev->base + CTRL0);
tsif_rx_enable = 1;
break;
}
case TSIF_STOP_RX:{
u32 tsif_ctrl0;
tsif_ctrl0 = davinci_readl(tsif_dev->base + CTRL0);
tsif_ctrl0 &=
~(TSIF_CTRL0_RCV_DMA_CTL | TSIF_CTRL0_RCV_CTL);
davinci_writel(tsif_ctrl0, tsif_dev->base + CTRL0);
tsif_rx_enable = 0;
break;
}
case TSIF_START_TX:{
u32 tsif_ctrl0;
void *addr;
addr =
(void *)davinci_readl(tsif_dev->base +
RRB0_STRT_ADD);
if (davinci_readl(tsif_dev->base + RRB0_STRT_ADD) ==
0x00000000)
return -EPERM;
tsif_ctrl0 = davinci_readl(tsif_dev->base + CTRL0);
tsif_ctrl0 |=
(TSIF_CTRL0_TX_DMA_CTL | TSIF_CTRL0_TX_CTL);
davinci_writel(tsif_ctrl0, tsif_dev->base + CTRL0);
tsif_tx_enable = 1;
break;
}
case TSIF_STOP_TX:{
u32 tsif_ctrl0;
tsif_ctrl0 = davinci_readl(tsif_dev->base + CTRL0);
tsif_ctrl0 &=
~(TSIF_CTRL0_TX_DMA_CTL | TSIF_CTRL0_TX_CTL);
davinci_writel(tsif_ctrl0, tsif_dev->base + CTRL0);
tsif_tx_enable = 0;
tsif_tx_ats_init = 0;
break;
}
case TSIF_CONFIG_PAT:{
unsigned char flag;
unsigned int pat_store_add;
get_user(flag, (unsigned char *)arg);
if (flag)
tsif_set_pat_config(inode, arg);
else {
davinci_writel(0x0, tsif_dev->base +
PAT_SENSE_CFG);
pat_store_add = (unsigned int)
phys_to_virt(davinci_readl
(tsif_dev->base +
PAT_STORE_ADD));
kfree((void *)pat_store_add);
}
break;
}
case TSIF_GET_PAT_PKT:{
unsigned int pat_store_add;
wait_for_completion_interruptible(&tsif_isr_data.
pat_complete);
pat_store_add =
davinci_readl(tsif_dev->base + PAT_STORE_ADD);
pat_store_add =
(unsigned int)phys_to_virt(pat_store_add);
/* copy to user the PAT packet */
if (copy_to_user
((void *)arg, (void *)pat_store_add, 192))
return -EFAULT;
else
return 0;
break;
} /* case */
case TSIF_GET_PAT_CONFIG:{
struct tsif_pat_config pat_cfg;
pat_cfg.flag = davinci_readl(tsif_dev->base +
PAT_SENSE_CFG) >> 16;
/* copy the configuration to the user space */
if (copy_to_user((struct tsif_pat_config *)arg,
&pat_cfg,
sizeof(struct tsif_pat_config)))
return -EFAULT;
break;
}
case TSIF_GET_PMT_CONFIG:{
struct tsif_pmt_config pmt_cfg;
pmt_cfg.pmt_pid = davinci_readl(tsif_dev->base +
PMT_SENSE_CFG) & 0x1fff;
pmt_cfg.flag = davinci_readl(tsif_dev->base +
PMT_SENSE_CFG) >> 16;
/* copy the configuration to the user space */
if (copy_to_user((struct tsif_pmt_config *)arg,
&pmt_cfg,
sizeof(struct tsif_pmt_config)))
return -EFAULT;
break;
}
case TSIF_CONFIG_PMT:{
struct tsif_pmt_config pmt_cfg;
unsigned int pmt_store_add;
if (copy_from_user(&pmt_cfg,
(struct tsif_pmt_config *)arg,
sizeof(struct tsif_pmt_config)))
return -EFAULT;
if (pmt_cfg.flag)
tsif_set_pmt_config(inode, arg);
else {
davinci_writel(0x0,
tsif_dev->base + PMT_SENSE_CFG);
pmt_store_add = (unsigned int)
phys_to_virt(davinci_readl
(tsif_dev->base +
PMT_STORE_ADD));
kfree((void *)pmt_store_add);
}
break;
}
case TSIF_GET_PMT_PKT:{
unsigned int pmt_store_add;
wait_for_completion_interruptible(&tsif_isr_data.
pmt_complete);
pmt_store_add =
davinci_readl(tsif_dev->base + PMT_STORE_ADD);
pmt_store_add =
(unsigned int)phys_to_virt(pmt_store_add);
/* copy to user the PMT packet */
if (copy_to_user
((void *)arg, (void *)pmt_store_add, 4096))
return -EFAULT;
else
return 0;
break;
}
case TSIF_ENABLE_PCR:{
tsif_set_pcr_config(inode, arg);
break;
}
case TSIF_DISABLE_PCR:{
davinci_writel(0x0, tsif_dev->base + PCR_SENSE_CFG);
break;
}
case TSIF_SET_SPCPKT_CONFIG:{
tsif_set_spec_pkt_config(inode, arg);
break;
}
case TSIF_GET_SPCPKT_CONFIG:{
struct tsif_spcpkt_config spcpkt_cfg;
char *spcpkt_cfg_buff_ptr;
if ((davinci_readl(tsif_dev->base + CTRL1) &
TSIF_CTRL1_STREAM_BNDRY_CTL) == 0)
spcpkt_cfg.pid = 0x2000; /* set illegal PID */
else
spcpkt_cfg.pid =
(u16) (davinci_readl
(tsif_dev->base + BSP_PID) & 0x1fff);
spcpkt_cfg_buff_ptr =
(u8 *) davinci_readl(tsif_dev->base +
BSP_STORE_ADD);
/* copy the configuration to the user space */
if (copy_to_user((struct tsif_spcpkt_config *)arg,
&spcpkt_cfg,
sizeof(struct tsif_spcpkt_config)))
return -EFAULT;
break;
}
case TSIF_SET_ATS:{
unsigned long ats_val;
get_user(ats_val, (int *)arg);
ats_val |= (1 << 30);
davinci_writel(ats_val, tsif_dev->base + TX_ATS_INIT);
break;
}
case TSIF_GET_ATS:{
unsigned int ats_val;
ats_val = davinci_readl(tsif_dev->base +
TX_ATS_MONITOR);
put_user(ats_val, (int *)arg);
break;
}
case TSIF_BYPASS_ENABLE:{
davinci_writel(0x01000000,
tsif_dev->base + BP_MODE_CFG);
break;
}
case TSIF_SET_CONSEQUENTIAL_MODE:{
unsigned int ctrl0;
ctrl0 = davinci_readl(tsif_dev->base + CTRL0);
ctrl0 |= TSIF_CTRL0_RCV_IF_MODE_DMA;
davinci_writel(ctrl0, tsif_dev->base + CTRL0);
break;
}
case TSIF_ENABLE_GOP_DETECT:{
unsigned char gop_flag;
get_user(gop_flag, (int *)arg);
if (gop_flag) {
davinci_writel(
(davinci_readl(
tsif_dev->base + INTEN) |
TSIF_INTEN_GOP_START_INTEN),
tsif_dev->base + INTEN);
davinci_writel(
(davinci_readl(
tsif_dev->base + INTEN_SET) |
TSIF_INTEN_SET_GOP_START_INTEN_SET),
tsif_dev->base + INTEN_SET);
davinci_writel(
(davinci_readl(
tsif_dev->base + CTRL1) | 0x20),
tsif_dev->base + CTRL1);
} else {
davinci_writel(
(davinci_readl(
tsif_dev->base + CTRL1) & 0xFFFFFFDF),
tsif_dev->base + CTRL1);
}
break;
}
case TSIF_GET_SPCPKT:{
unsigned int bsp_store_add;
wait_for_completion_interruptible(&tsif_isr_data.
spcpkt_complete);
bsp_store_add =
davinci_readl(tsif_dev->base + BSP_STORE_ADD);
bsp_store_add =
(unsigned int)phys_to_virt(bsp_store_add);
/* copy to user the specific packet */
if (copy_to_user
((void *)arg, (void *)bsp_store_add, 4096))
return -EFAULT;
else
return 0;
break;
}
case TSIF_SET_ENDIAN_CTL:{
unsigned long endian_ctl;
unsigned long cur_reg_val;
get_user(endian_ctl, (int *)arg);
cur_reg_val = davinci_readl(tsif_dev->base + CTRL1);
if (endian_ctl)
cur_reg_val |= 1 << 14;
else
cur_reg_val &= ~(1 << 14);
davinci_writel(cur_reg_val, tsif_dev->base + CTRL1);
break;
}
}
return ret;
}
int tsif_set_rx_config(struct inode *inode, unsigned long arg)
{
struct tsif_control_dev *tsif_dev;
unsigned int index, minor = iminor(inode);
u32 tsif_ctrl0, tsif_ctrl1, inten;
u32 rx_ctrl0, rx_ctrl1;
struct tsif_rx_config rx_cfg;
int pkt_size = 0;
index = minor / tsif_control_minor_count;
tsif_dev = tsif_control_dev_get_by_major(index);
tsif_ctrl0 = davinci_readl(tsif_dev->base + CTRL0);
/* copy the parameters to the configuration */
if (copy_from_user(&rx_cfg,
(struct tsif_rx_config *)arg,
sizeof(struct tsif_rx_config)))
return -EFAULT;
if (tsif_stop_rx(inode) != 0)
return -EPERM;
davinci_writel(TSIF_RING_BUFFER_WRITE_CHANNEL_CONTROL_RESETVAL,
tsif_dev->base + WRB_CH_CTRL);
/* Disbale all receiver relarted interrupts */
inten = davinci_readl(tsif_dev->base + INTEN);
inten &= ~(TSIF_INTEN_RBW7_FULL_INTEN |
TSIF_INTEN_RBW6_FULL_INTEN |
TSIF_INTEN_RBW5_FULL_INTEN |
TSIF_INTEN_RBW4_FULL_INTEN |
TSIF_INTEN_RBW3_FULL_INTEN |
TSIF_INTEN_RBW2_FULL_INTEN |
TSIF_INTEN_RBW1_FULL_INTEN |
TSIF_INTEN_RBW0_FULL_INTEN | TSIF_INTEN_GOP_START_INTEN);
davinci_writel(inten, tsif_dev->base + INTEN);
if (&rx_cfg != NULL) {
rx_ctrl0 = rx_ctrl1 = 0x00000000;
switch (rx_cfg.if_mode) {
case TSIF_IF_SERIAL_SYNC:
rx_ctrl0 |= TSIF_CTRL0_RCV_IF_MODE_SER_SYN;
break;
case TSIF_IF_SERIAL_ASYNC:
rx_ctrl0 |= TSIF_CTRL0_RCV_IF_MODE_SER_ASYN;
break;
case TSIF_IF_PARALLEL_SYNC:
rx_ctrl0 |= TSIF_CTRL0_RCV_IF_MODE_PAR_SYN;
break;
case TSIF_IF_PARALLEL_ASYNC:
rx_ctrl0 |= TSIF_CTRL0_RCV_IF_MODE_PAR_ASYN;
break;
case TSIF_IF_DMA:
rx_ctrl0 |= TSIF_CTRL0_RCV_IF_MODE_DMA;
break;
default:
return -EINVAL;
}
switch (rx_cfg.filter_mode) {
case TSIF_PID_FILTER_BYPASS:{
switch (rx_cfg.stream_mode) {
case TSIF_STREAM_TS:
rx_ctrl0 |=
TSIF_CTRL0_RCV_STREAM_MODE_TS_ACTIVE;
pkt_size = 192;
break;
case TSIF_STREAM_NON_TS:
rx_ctrl0 |=
TSIF_CTRL0_RCV_STREAM_MODE_TS_INACTIVE;
switch (rx_cfg.pkt_size) {
case TSIF_200_BYTES_PER_PKT:
rx_ctrl0 |=
TSIF_CTRL0_RCV_PKT_SIZE_BYTE_200;
pkt_size = 200;
break;
case TSIF_208_BYTES_PER_PKT:
rx_ctrl0 |=
TSIF_CTRL0_RCV_PKT_SIZE_BYTE_208;
pkt_size = 208;
break;
case TSIF_216_BYTES_PER_PKT:
rx_ctrl0 |=
TSIF_CTRL0_RCV_PKT_SIZE_BYTE_216;
pkt_size = 216;
break;
case TSIF_224_BYTES_PER_PKT:
rx_ctrl0 |=
TSIF_CTRL0_RCV_PKT_SIZE_BYTE_224;
pkt_size = 224;
break;
case TSIF_232_BYTES_PER_PKT:
rx_ctrl0 |=
TSIF_CTRL0_RCV_PKT_SIZE_BYTE_232;
pkt_size = 232;
break;
case TSIF_240_BYTES_PER_PKT:
rx_ctrl0 |=
TSIF_CTRL0_RCV_PKT_SIZE_BYTE_240;
pkt_size = 240;
break;
case TSIF_248_BYTES_PER_PKT:
rx_ctrl0 |=
TSIF_CTRL0_RCV_PKT_SIZE_BYTE_248;
pkt_size = 248;
break;
case TSIF_256_BYTES_PER_PKT:
rx_ctrl0 |=
TSIF_CTRL0_RCV_PKT_SIZE_BYTE_256;
pkt_size = 256;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
break;
}
case TSIF_PID_FILTER_FULL_MANUAL:
rx_ctrl1 |=
TSIF_CTRL1_STREAM_BNDRY_CTL |
TSIF_CTRL1_PID_FILTER_EN_ACTIVATE |
TSIF_CTRL1_PID_FILTER_CTL_FULL_MAN;
rx_ctrl0 |= TSIF_CTRL0_RCV_STREAM_MODE_TS_ACTIVE;
pkt_size = 192;
break;
case TSIF_PID_FILTER_SEMI_AUTO_A:
rx_ctrl1 |=
TSIF_CTRL1_STREAM_BNDRY_CTL |
TSIF_CTRL1_PID_FILTER_EN_ACTIVATE |
TSIF_CTRL1_PID_FILTER_CTL_SEMI_A;
rx_ctrl0 |= TSIF_CTRL0_RCV_STREAM_MODE_TS_ACTIVE;
pkt_size = 192;
break;
case TSIF_PID_FILTER_SEMI_AUTO_B:
rx_ctrl1 |=
TSIF_CTRL1_STREAM_BNDRY_CTL |
TSIF_CTRL1_PID_FILTER_EN_ACTIVATE |
TSIF_CTRL1_PID_FILTER_CTL_SEMI_B;
rx_ctrl0 |= TSIF_CTRL0_RCV_STREAM_MODE_TS_ACTIVE;
pkt_size = 192;
break;
case TSIF_PID_FILTER_FULL_AUTO:
rx_ctrl1 |=
TSIF_CTRL1_STREAM_BNDRY_CTL |
TSIF_CTRL1_PID_FILTER_EN_ACTIVATE |
TSIF_CTRL1_PID_FILTER_CTL_FULL_AUT;
rx_ctrl0 |= TSIF_CTRL0_RCV_STREAM_MODE_TS_ACTIVE;
pkt_size = 192;
break;
default:
return -EINVAL;
}
switch (rx_cfg.ats_mode) {
case TSIF_RX_ATS_THROUGH:
rx_ctrl0 |= TSIF_CTRL0_RCV_ATS_MODE_IN_192;
break;
case TSIF_RX_ATS_NOADD:
rx_ctrl0 |= TSIF_CTRL0_RCV_ATS_MODE_IN_188;
break;
case TSIF_RX_ATS_CHANGE:
rx_ctrl0 |= TSIF_CTRL0_RCV_ATS_MODE_CHANGE_192;
break;
case TSIF_RX_ATS_ADD:
rx_ctrl0 |= TSIF_CTRL0_RCV_ATS_MODE_ADD_188;
break;
default:
return -EINVAL;
}
tsif_ctrl0 = davinci_readl(tsif_dev->base + CTRL0);
tsif_ctrl0 &= ~(RX_CONFIG);
tsif_ctrl0 |= rx_ctrl0;
davinci_writel(tsif_ctrl0, tsif_dev->base + CTRL0);
tsif_ctrl1 = davinci_readl(tsif_dev->base + CTRL1);
tsif_ctrl1 |= rx_ctrl1;
davinci_writel(tsif_ctrl1, tsif_dev->base + CTRL1);
} else {
tsif_ctrl0 = davinci_readl(tsif_dev->base + CTRL0);
tsif_ctrl0 &= ~(RX_CONFIG) | 0x00000000;
davinci_writel(tsif_ctrl0, tsif_dev->base + CTRL0);
tsif_ctrl1 = davinci_readl(tsif_dev->base + CTRL1);
tsif_ctrl1 &= ~(TSIF_CTRL1_PID_FILTER_CTL) | 0x00000000;
davinci_writel(tsif_ctrl1, tsif_dev->base + CTRL1);
}
return 0;
}
int tsif_set_tx_config(struct inode *inode, unsigned long arg)
{
struct tsif_control_dev *tsif_dev;
unsigned int index, minor = iminor(inode);
u32 tx_ctrl, tsif_ctrl0, inten;
struct tsif_tx_config tx_cfg;
int pkt_size = 0;
index = minor / tsif_control_minor_count;
tsif_dev = tsif_control_dev_get_by_major(index);
tsif_ctrl0 = davinci_readl(tsif_dev->base + CTRL0);
/* copy the parameters to the configuration */
if (copy_from_user(&tx_cfg,
(struct tsif_tx_config *)arg,
sizeof(struct tsif_tx_config)))
return -EFAULT;
davinci_writel(TSIF_RING_BUF_RD_CH_CTL_RESETVAL,
tsif_dev->base + RRB_CH_CTRL);
inten = davinci_readl(tsif_dev->base + INTEN);
inten &= ~TSIF_INTEN_RBR0_FULL_INTEN;
davinci_writel(inten, tsif_dev->base + INTEN);
if (&tx_cfg != NULL) {
tx_ctrl = 0x00000000;
switch (tx_cfg.if_mode) {
case TSIF_IF_SERIAL_SYNC:
if (tx_cfg.clk_speed == TSIF_13_5_MHZ_SERIAL_PARALLEL)
set_tsif_clk(TSIF_13_5_MHZ_SERIAL_PARALLEL);
else if (tx_cfg.clk_speed ==
TSIF_16_875_MHZ_SERIAL_PARALLEL)
set_tsif_clk(TSIF_16_875_MHZ_SERIAL_PARALLEL);
else if (tx_cfg.clk_speed == TSIF_27_0_MHZ_SERIAL)
set_tsif_clk(TSIF_27_0_MHZ_SERIAL);
else if (tx_cfg.clk_speed == TSIF_54_0_MHZ_SERIAL)
set_tsif_clk(TSIF_54_0_MHZ_SERIAL);
else if (tx_cfg.clk_speed == TSIF_81_0_MHZ_SERIAL)
set_tsif_clk(TSIF_81_0_MHZ_SERIAL);
else
return -EINVAL;
davinci_cfg_reg(DM646X_PTSOMUX_SERIAL);
davinci_cfg_reg(DM646X_PTSIMUX_SERIAL);
tx_ctrl |= TSIF_CTRL0_TX_IF_MODE_SER_SYN;
break;
case TSIF_IF_SERIAL_ASYNC:
if (tx_cfg.clk_speed == TSIF_13_5_MHZ_SERIAL_PARALLEL)
set_tsif_clk(TSIF_13_5_MHZ_SERIAL_PARALLEL);
else if (tx_cfg.clk_speed ==
TSIF_16_875_MHZ_SERIAL_PARALLEL)
set_tsif_clk(TSIF_16_875_MHZ_SERIAL_PARALLEL);
else if (tx_cfg.clk_speed == TSIF_27_0_MHZ_SERIAL)
set_tsif_clk(TSIF_27_0_MHZ_SERIAL);
else if (tx_cfg.clk_speed == TSIF_54_0_MHZ_SERIAL)
set_tsif_clk(TSIF_54_0_MHZ_SERIAL);
else if (tx_cfg.clk_speed == TSIF_81_0_MHZ_SERIAL)
set_tsif_clk(TSIF_81_0_MHZ_SERIAL);
else
return -EINVAL;
davinci_cfg_reg(DM646X_PTSOMUX_SERIAL);
davinci_cfg_reg(DM646X_PTSIMUX_SERIAL);
tx_ctrl |= TSIF_CTRL0_TX_IF_MODE_SER_ASYN;
break;
case TSIF_IF_PARALLEL_SYNC:
if (tx_cfg.clk_speed == TSIF_13_5_MHZ_SERIAL_PARALLEL)
set_tsif_clk(TSIF_13_5_MHZ_SERIAL_PARALLEL);
else if (tx_cfg.clk_speed ==
TSIF_16_875_MHZ_SERIAL_PARALLEL)
set_tsif_clk(TSIF_16_875_MHZ_SERIAL_PARALLEL);
else
return -EINVAL;
davinci_cfg_reg(DM646X_PTSOMUX_PARALLEL);
davinci_cfg_reg(DM646X_PTSIMUX_PARALLEL);
tx_ctrl |= TSIF_CTRL0_TX_IF_MODE_PAR_SYN;
break;
case TSIF_IF_PARALLEL_ASYNC:
if (tx_cfg.clk_speed == TSIF_13_5_MHZ_SERIAL_PARALLEL)
set_tsif_clk(TSIF_13_5_MHZ_SERIAL_PARALLEL);
else if (tx_cfg.clk_speed ==
TSIF_16_875_MHZ_SERIAL_PARALLEL)
set_tsif_clk(TSIF_16_875_MHZ_SERIAL_PARALLEL);
else
return -EINVAL;
davinci_cfg_reg(DM646X_PTSOMUX_PARALLEL);
davinci_cfg_reg(DM646X_PTSIMUX_PARALLEL);
tx_ctrl |= TSIF_CTRL0_TX_IF_MODE_PAR_ASYN;
break;
case TSIF_IF_DMA:
default:
return -EINVAL;
}
switch (tx_cfg.stream_mode) {
case TSIF_STREAM_TS:
tx_ctrl |= TSIF_CTRL0_TX_STREAM_MODE_TS_ACTIVE;
pkt_size = 192;
break;
case TSIF_STREAM_NON_TS:
tx_ctrl |= TSIF_CTRL0_TX_STREAM_MODE_TS_INACTIVE;
switch (tx_cfg.pkt_size) {
case TSIF_200_BYTES_PER_PKT:
tx_ctrl |= TSIF_CTRL0_TX_PKT_SIZE_BYTE_200;
pkt_size = 200;
break;
case TSIF_208_BYTES_PER_PKT:
tx_ctrl |= TSIF_CTRL0_TX_PKT_SIZE_BYTE_208;
pkt_size = 208;
break;
case TSIF_216_BYTES_PER_PKT:
tx_ctrl |= TSIF_CTRL0_TX_PKT_SIZE_BYTE_216;
pkt_size = 216;
break;
case TSIF_224_BYTES_PER_PKT:
tx_ctrl |= TSIF_CTRL0_TX_PKT_SIZE_BYTE_224;
pkt_size = 224;
break;
case TSIF_232_BYTES_PER_PKT:
tx_ctrl |= TSIF_CTRL0_TX_PKT_SIZE_BYTE_232;
pkt_size = 232;
break;
case TSIF_240_BYTES_PER_PKT:
tx_ctrl |= TSIF_CTRL0_TX_PKT_SIZE_BYTE_240;
pkt_size = 240;
break;
case TSIF_248_BYTES_PER_PKT:
tx_ctrl |= TSIF_CTRL0_TX_PKT_SIZE_BYTE_248;
pkt_size = 248;
break;
case TSIF_256_BYTES_PER_PKT:
tx_ctrl |= TSIF_CTRL0_TX_PKT_SIZE_BYTE_256;
pkt_size = 256;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
switch (tx_cfg.ats_mode) {
case TSIF_TX_ATS_REMOVE:
tx_ctrl |= TSIF_CTRL0_TX_ATS_MODE_OUT_188;
break;
case TSIF_TX_ATS_THROUGH:
tx_ctrl |= TSIF_CTRL0_TX_ATS_MODE_OUT_192;
break;
default:
return -EINVAL;
}
davinci_writel((u32) tx_cfg.interval_wait,
tsif_dev->base + ASYNC_TX_WAIT);
tsif_ctrl0 = davinci_readl(tsif_dev->base + CTRL0);
tsif_ctrl0 &= ~(TX_CONFIG);
tsif_ctrl0 |= tx_ctrl;
tsif_ctrl0 |= TSIF_CTRL0_TX_CLK_INV_MASK;
davinci_writel(tsif_ctrl0, tsif_dev->base + CTRL0);
} else {
davinci_writel(TSIF_ASYNC_TX_WAIT_RESETVAL,
tsif_dev->base + ASYNC_TX_WAIT);
tsif_ctrl0 = davinci_readl(tsif_dev->base + CTRL0);
tsif_ctrl0 &= ~(TX_CONFIG) | 0x00000000;
davinci_writel(tsif_ctrl0, tsif_dev->base + CTRL0);
}
/* Clear RBR0_full */
davinci_writel(TSIF_INTEN_CLR_RBR0_FULL_INTEN_CLR,
tsif_dev->base + INT_STATUS_CLR);
/* RBR0_full_inten<-1 */
inten = davinci_readl(tsif_dev->base + INTEN);
inten |= TSIF_INTEN_RBR0_FULL_INTEN;
davinci_writel(inten, tsif_dev->base + INTEN);
/* RBR0_full_inten_set<-1 */
inten = davinci_readl(tsif_dev->base + INTEN_SET);
inten |= TSIF_INTEN_SET_RBR0_FULL_INTEN_SET;
davinci_writel(inten, tsif_dev->base + INTEN_SET);
return 0;
}
/* register access routines */
static inline u32 regr_bl(u32 offset)
{
return davinci_readl(vpss_base_addr + offset);
}
