void MstarSysInit(void)
{
uint u32Tmp;
/*set up Mstar IRQ handler*/
extern void mhal_fiq_merge(void);
extern void MAsm_CPU_TimerStart(void);
extern void dcache_init(void);
extern void l2_cache_init(void);
mhal_fiq_merge();
MsOS_Init();
#ifdef CONFIG_SYS_DCACHE
dcache_init();
#endif
#ifndef CONFIG_L2_OFF
l2_cache_init();
#endif
#if defined(CONFIG_TIMER_TEST)
MDrv_Timer_ISR_Register();
#endif
MsOS_CPU_EnableInterrupt();
MAsm_CPU_TimerStart();
MDrv_MMIO_Init();
MDrv_MMIO_GetBASE((MS_U32 *)&MS_RIU_MAP, (MS_U32 *)&u32Tmp, MS_MODULE_PM);
#if (ENABLE_MODULE_ENV_IN_SERIAL==1)
puts ("SPI: ");
{
extern int spi_init (void);
spi_init(); /* go init the SPI */
}
#if (CONFIG_MSTAR_BD_MST028B_10AFX_EAGLE||CONFIG_MSTAR_BD_MST038B_10AHT_EAGLE)
MDrv_SERFLASH_SetWPInfo(TRUE);
#else
ms_Flash_SetHWWP_CB pCB = msFlash_ActiveFlash_Set_HW_WP;
MDrv_SERFLASH_SetFlashWPCallBack(pCB);
FlashSetHWWPCB = FlashSetHWWPCB;
McuChipSelectCB = McuChipSelectCB;
#endif
#else
#if(ENABLE_BOOTING_FROM_EXT_EMMC_WITH_CPU==0)
MDrv_SERFLASH_Init();
#endif
#endif
mdrv_gpio_init();
MDrv_BDMA_Init(MIU_INTERVAL);
run_command("init_raw_io" , 0);
run_command("config_raw_io" , 0);
}
DCACHE *
target_dcache_get_or_init (void)
{
DCACHE *dcache
= target_dcache_aspace_key.get (current_program_space->aspace);
if (dcache == NULL)
{
dcache = dcache_init ();
target_dcache_aspace_key.set (current_program_space->aspace, dcache);
}
return dcache;
}
DCACHE *
target_dcache_get_or_init (void)
{
DCACHE *dcache
= (DCACHE *) address_space_data (current_program_space->aspace,
target_dcache_aspace_key);
if (dcache == NULL)
{
dcache = dcache_init ();
set_address_space_data (current_program_space->aspace,
target_dcache_aspace_key, dcache);
}
return dcache;
}
asmlinkage void __init start_kernel(void)
{
char * command_line;
#ifdef __SMP__
static int boot_cpu = 1;
/* "current" has been set up, we need to load it now */
if (!boot_cpu)
initialize_secondary();
boot_cpu = 0;
#endif
/*
* Interrupts are still disabled. Do necessary setups, then
* enable them
*/
printk(linux_banner);
setup_arch(&command_line, &memory_start, &memory_end);
memory_start = paging_init(memory_start,memory_end);
trap_init();
init_IRQ();
sched_init();
time_init();
parse_options(command_line);
/*
* HACK ALERT! This is early. We're enabling the console before
* we've done PCI setups etc, and console_init() must be aware of
* this. But we do want output early, in case something goes wrong.
*/
memory_start = console_init(memory_start,memory_end);
#ifdef CONFIG_MODULES
init_modules();
#endif
if (prof_shift) {
prof_buffer = (unsigned int *) memory_start;
/* only text is profiled */
prof_len = (unsigned long) &_etext - (unsigned long) &_stext;
prof_len >>= prof_shift;
memory_start += prof_len * sizeof(unsigned int);
memset(prof_buffer, 0, prof_len * sizeof(unsigned int));
}
#ifdef CONFIG_REMOTE_DEBUG
set_debug_traps();
/* breakpoint(); */ /* execute a BREAK insn */
#endif
memory_start = kmem_cache_init(memory_start, memory_end);
sti();
calibrate_delay();
#ifdef CONFIG_CPU_R5900
r5900_init();
#endif
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start && !initrd_below_start_ok && initrd_start < memory_start) {
printk(KERN_CRIT "initrd overwritten (0x%08lx < 0x%08lx) - "
"disabling it.\n",initrd_start,memory_start);
initrd_start = 0;
}
#endif
#ifdef CONFIG_BINFMT_IRIX
init_inventory ();
#endif
mem_init(memory_start,memory_end);
kmem_cache_sizes_init();
#ifdef CONFIG_PROC_FS
proc_root_init();
#endif
uidcache_init();
filescache_init();
dcache_init();
vma_init();
buffer_init();
signals_init();
inode_init();
file_table_init();
#if defined(CONFIG_SYSVIPC)
ipc_init();
#endif
#if defined(CONFIG_QUOTA)
dquot_init_hash();
#endif
check_bugs();
printk("POSIX conformance testing by UNIFIX\n");
/*
* We count on the initial thread going ok
* Like idlers init is an unlocked kernel thread, which will
* make syscalls (and thus be locked).
*/
smp_init();
kernel_thread(init, NULL, CLONE_FS | CLONE_FILES | CLONE_SIGHAND);
current->need_resched = 1;
cpu_idle(NULL);
}
