static int dcon_init_xo_1_5(struct dcon_priv *dcon) { unsigned int irq; u_int8_t tmp; struct pci_dev *pdev; pdev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855, NULL); if (!pdev) { pr_err("cannot find VX855 PCI ID\n"); return 1; } pci_read_config_byte(pdev, 0x95, &tmp); pci_write_config_byte(pdev, 0x95, tmp|0x0c); /* Set GPIO8 to GPIO mode, not SSPICLK */ pci_read_config_byte(pdev, 0xe3, &tmp); pci_write_config_byte(pdev, 0xe3, tmp | 0x04); /* Set GPI10/GPI11 to GPI mode, not SSPISDI/SSPISS */ pci_read_config_byte(pdev, 0xe4, &tmp); pci_write_config_byte(pdev, 0xe4, tmp|0x08); /* clear PMU_RxE1[6] to select SCI on GPIO12 */ /* clear PMU_RxE0[6] to choose falling edge */ pci_read_config_byte(pdev, 0xe1, &tmp); pci_write_config_byte(pdev, 0xe1, tmp & ~BIT_GPIO12); pci_read_config_byte(pdev, 0xe0, &tmp); pci_write_config_byte(pdev, 0xe0, tmp & ~BIT_GPIO12); dcon_clear_irq(); /* set PMIO_Rx52[6] to enable SCI/SMI on gpio12 */ outb(inb(VX855_GPI_SCI_SMI)|BIT_GPIO12, VX855_GPI_SCI_SMI); /* Determine the current state of DCONLOAD, likely set by firmware */ /* GPIO1 */ dcon->curr_src = (inl(VX855_GENL_PURPOSE_OUTPUT) & 0x1000) ? DCON_SOURCE_CPU : DCON_SOURCE_DCON; dcon->pending_src = dcon->curr_src; pci_dev_put(pdev); /* we're sharing the IRQ with ACPI */ irq = acpi_gbl_FADT.sci_interrupt; if (request_irq(irq, &dcon_interrupt, IRQF_SHARED, "DCON", dcon)) { pr_err("DCON (IRQ%d) allocation failed\n", irq); return 1; } return 0; }
static int dcon_init_xo_1_5(struct dcon_priv *dcon) { unsigned int irq; u_int8_t tmp; struct pci_dev *pdev; pdev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855, NULL); if (!pdev) { printk(KERN_ERR "cannot find VX855 PCI ID\n"); return 1; } pci_read_config_byte(pdev, 0x95, &tmp); pci_write_config_byte(pdev, 0x95, tmp|0x0c); /* */ pci_read_config_byte(pdev, 0xe3, &tmp); pci_write_config_byte(pdev, 0xe3, tmp | 0x04); /* */ pci_read_config_byte(pdev, 0xe4, &tmp); pci_write_config_byte(pdev, 0xe4, tmp|0x08); /* */ /* */ pci_read_config_byte(pdev, 0xe1, &tmp); pci_write_config_byte(pdev, 0xe1, tmp & ~BIT_GPIO12); pci_read_config_byte(pdev, 0xe0, &tmp); pci_write_config_byte(pdev, 0xe0, tmp & ~BIT_GPIO12); dcon_clear_irq(); /* */ outb(inb(VX855_GPI_SCI_SMI)|BIT_GPIO12, VX855_GPI_SCI_SMI); /* */ /* */ dcon->curr_src = (inl(VX855_GENL_PURPOSE_OUTPUT) & 0x1000) ? DCON_SOURCE_CPU : DCON_SOURCE_DCON; dcon->pending_src = dcon->curr_src; pci_dev_put(pdev); /* */ irq = acpi_gbl_FADT.sci_interrupt; if (request_irq(irq, &dcon_interrupt, IRQF_SHARED, "DCON", dcon)) { printk(KERN_ERR PREFIX "DCON (IRQ%d) allocation failed\n", irq); return 1; } return 0; }
static int dcon_read_status_xo_1_5(u8 *status) { if (!dcon_was_irq()) return -1; /* i believe this is the same as "inb(0x44b) & 3" */ *status = gpio_get_value(VX855_GPI(10)); *status |= gpio_get_value(VX855_GPI(11)) << 1; dcon_clear_irq(); return 0; }
static int dcon_read_status_xo_1_5(u8 *status) { if (!dcon_was_irq()) return -1; /* */ *status = gpio_get_value(VX855_GPI(10)); *status |= gpio_get_value(VX855_GPI(11)) << 1; dcon_clear_irq(); return 0; }
static u8 dcon_read_status_xo_1_5(void) { u8 status; if (!dcon_was_irq()) return -1; /* i believe this is the same as "inb(0x44b) & 3" */ status = gpio_get_value(VX855_GPI(10)); status |= gpio_get_value(VX855_GPI(11)) << 1; dcon_clear_irq(); return status; }
static int dcon_init_xo_1_5(struct dcon_priv *dcon) { unsigned int irq; dcon_clear_irq(); /* set PMIO_Rx52[6] to enable SCI/SMI on gpio12 */ outb(inb(VX855_GPI_SCI_SMI)|BIT_GPIO12, VX855_GPI_SCI_SMI); /* Determine the current state of DCONLOAD, likely set by firmware */ /* GPIO1 */ dcon->curr_src = (inl(VX855_GENL_PURPOSE_OUTPUT) & 0x1000) ? DCON_SOURCE_CPU : DCON_SOURCE_DCON; dcon->pending_src = dcon->curr_src; /* we're sharing the IRQ with ACPI */ irq = acpi_gbl_FADT.sci_interrupt; if (request_irq(irq, &dcon_interrupt, IRQF_SHARED, "DCON", dcon)) { pr_err("DCON (IRQ%d) allocation failed\n", irq); return 1; } return 0; }