static unsigned int is_reg_addr_valid(unsigned int isVa, unsigned long addr) { unsigned int i = 0; for (i = 0; i < DISP_REG_NUM; i++) { if ((isVa == 1) && (addr >= dispsys_reg[i]) && (addr <= dispsys_reg[i] + 0x1000)) break; if ((isVa == 0) && (addr >= ddp_reg_pa_base[i]) && (addr <= ddp_reg_pa_base[i] + 0x1000)) break; } if (i < DISP_REG_NUM) { DDPMSG("addr valid, isVa=0x%x, addr=0x%lx, module=%s!\n", isVa, addr, ddp_get_reg_module_name(i)); return 1; } else { DDPERR("is_reg_addr_valid return fail, isVa=0x%x, addr=0x%lx!\n", isVa, addr); return 0; } }
static void process_dbg_opt(const char *opt) { char *buf = dbg_buf + strlen(dbg_buf); static disp_session_config config; if (0 == strncmp(opt, "regr:", 5)) { char *p = (char *)opt + 5; unsigned long addr = (unsigned long) simple_strtoul(p, &p, 16); if(is_reg_addr_valid(1, addr)==1)// (addr >= 0xf0000000U && addr <= 0xff000000U) { unsigned int regVal = DISP_REG_GET(addr); DDPMSG("regr: 0x%lx = 0x%08X\n", addr, regVal); sprintf(buf, "regr: 0x%lx = 0x%08X\n", addr, regVal); } else { sprintf(buf, "regr, invalid address 0x%lx\n", addr); goto Error; } } else if (0 == strncmp(opt, "regw:", 5)) { char *p = (char *)opt + 5; unsigned long addr = (unsigned long) simple_strtoul(p, &p, 16); unsigned int val = (unsigned int) simple_strtoul(p + 1, &p, 16); if(is_reg_addr_valid(1, addr)==1)// (addr >= 0xf0000000U && addr <= 0xff000000U) { unsigned int regVal; DISP_CPU_REG_SET(addr, val); regVal = DISP_REG_GET(addr); DDPMSG("regw: 0x%lx, 0x%08X = 0x%08X\n", addr, val, regVal); sprintf(buf, "regw: 0x%lx, 0x%08X = 0x%08X\n", addr, val, regVal); } else { sprintf(buf, "regw, invalid address 0x%lx \n", addr); goto Error; } } else if (0 == strncmp(opt, "dbg_log:", 8)) { char *p = (char *)opt + 8; unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10); if (enable) dbg_log_level = 1; else dbg_log_level = 0; sprintf(buf, "dbg_log: %d\n", dbg_log_level); } else if (0 == strncmp(opt, "irq_log:", 8)) { char *p = (char *)opt + 8; unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10); if (enable) irq_log_level = 1; else irq_log_level = 0; sprintf(buf, "irq_log: %d\n", irq_log_level); } else if (0 == strncmp(opt, "met_on:", 7)) { char *p = (char *)opt + 7; int met_on = (int) simple_strtoul(p, &p, 10); int rdma0_mode = (int) simple_strtoul(p + 1, &p, 10); int rdma1_mode = (int) simple_strtoul(p + 1, &p, 10); // ddp_init_met_tag(met_on,rdma0_mode,rdma1_mode); DDPMSG("process_dbg_opt, met_on=%d,rdma0_mode %d, rdma1 %d \n", met_on,rdma0_mode,rdma1_mode); sprintf(buf, "met_on:%d,rdma0_mode:%d,rdma1_mode:%d\n", met_on,rdma0_mode,rdma1_mode); } else if (0 == strncmp(opt, "backlight:", 10)) { char *p = (char *)opt + 10; unsigned int level = (unsigned int) simple_strtoul(p, &p, 10); if (level) { disp_bls_set_backlight(level); sprintf(buf, "backlight: %d\n", level); } else { goto Error; } } else if (0 == strncmp(opt, "pwm0:", 5) || 0 == strncmp(opt, "pwm1:", 5)) { char *p = (char *)opt + 5; unsigned int level = (unsigned int)simple_strtoul(p, &p, 10); if (level) { disp_pwm_id_t pwm_id = DISP_PWM0; if (opt[3] == '1') pwm_id = DISP_PWM1; disp_pwm_set_backlight(pwm_id, level); sprintf(buf, "PWM 0x%x : %d\n", pwm_id, level); } else { goto Error; } } else if (0 == strncmp(opt, "aal_dbg:", 8)) { aal_dbg_en = (int)simple_strtoul(opt + 8, NULL, 10); sprintf(buf, "aal_dbg_en = 0x%x\n", aal_dbg_en); } else if (0 == strncmp(opt, "dump_reg:", 9)) { char *p = (char *)opt + 9; unsigned int module = (unsigned int) simple_strtoul(p, &p, 10); DDPMSG("process_dbg_opt, module=%d \n", module); if (module<DISP_MODULE_NUM) { ddp_dump_reg(module); sprintf(buf, "dump_reg: %d\n", module); } else { DDPMSG("process_dbg_opt2, module=%d \n", module); goto Error; } } else if (0 == strncmp(opt, "dump_path:", 10)) { char *p = (char *)opt + 10; unsigned int mutex_idx = (unsigned int) simple_strtoul(p, &p, 10); DDPMSG("process_dbg_opt, path mutex=%d \n", mutex_idx); dpmgr_debug_path_status(mutex_idx); sprintf(buf, "dump_path: %d\n", mutex_idx); } else if (0 == strncmp(opt, "debug:", 6)) { char *p = (char *)opt + 6; unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10); if(enable==1) { DDPMSG("[DDP] debug=1, trigger AEE\n"); //aee_kernel_exception("DDP-TEST-ASSERT", "[DDP] DDP-TEST-ASSERT"); } else if(enable==2) { ddp_mem_test(); } else if(enable==3) { ddp_lcd_test(); } else if(enable==4) { //DDPAEE("test 4"); } else if(enable==5) { extern unsigned int gDDPError; if(gDDPError==0) gDDPError = 1; else gDDPError = 0; sprintf(buf, "bypass PQ: %d\n", gDDPError); DDPMSG("bypass PQ: %d\n", gDDPError); } else if(enable==6) { unsigned int i = 0; int * modules = ddp_get_scenario_list(DDP_SCENARIO_PRIMARY_DISP); int module_num = ddp_get_module_num(DDP_SCENARIO_PRIMARY_DISP); printk("dump path status:"); for(i=0;i<module_num;i++) { printk("%s-", ddp_get_module_name(modules[i])); } printk("\n"); ddp_dump_analysis(DISP_MODULE_CONFIG); ddp_dump_analysis(DISP_MODULE_MUTEX); for( i=0; i< module_num;i++) { ddp_dump_analysis(modules[i]); } ddp_dump_reg(DISP_MODULE_CONFIG); ddp_dump_reg(DISP_MODULE_MUTEX); for( i=0; i< module_num;i++) { ddp_dump_reg(modules[i]); } } else if(enable==7) { if(dbg_log_level<3) dbg_log_level++; else dbg_log_level=0; printk("DDP: dbg_log_level=%d\n", dbg_log_level); sprintf(buf, "dbg_log_level: %d\n", dbg_log_level); } #if 0 else if(enable==8) { DDPDUMP("clock_mm setting:%u \n", DISP_REG_GET(DISP_REG_CONFIG_C11)); if(DISP_REG_GET(DISP_REG_CONFIG_C11)&0xff000000!=0xff000000) { DDPDUMP("error, MM clock bit 24~bit31 should be 1, but real value=0x%x", DISP_REG_GET(DISP_REG_CONFIG_C11)); } } #endif else if(enable==9) { gOVLBackground = 0xFF0000FF; printk("DDP: gOVLBackground=%d\n", gOVLBackground); sprintf(buf, "gOVLBackground: %d\n", gOVLBackground); } else if(enable==10) { gOVLBackground = 0xFF000000; printk("DDP: gOVLBackground=%d\n", gOVLBackground); sprintf(buf, "gOVLBackground: %d\n", gOVLBackground); } else if(enable==11) { unsigned int i=0; for(i=0;i<DISP_REG_NUM;i++) { DDPDUMP("i=%d, module=%s, reg_va=0x%lx\n", i, ddp_get_reg_module_name(i), dispsys_reg[i]); } } else if(enable==12) { if(gUltraEnable==0) gUltraEnable = 1; else gUltraEnable = 0; printk("DDP: gUltraEnable=%d\n", gUltraEnable); sprintf(buf, "gUltraEnable: %d\n", gUltraEnable); } } else if (0 == strncmp(opt, "mmp", 3)) { init_ddp_mmp_events(); } else { dbg_buf[0]='\0'; goto Error; } return; Error: DDPERR("parse command error!\n%s\n\n%s", opt, STR_HELP); }
static int disp_probe(struct platform_device *pdev) { struct class_device; int ret; int i; int new_count; static unsigned int disp_probe_cnt = 0; if(disp_probe_cnt!=0) { return 0; } #if defined(CONFIG_TRUSTONIC_TEE_SUPPORT) && (CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) disp_misc_dev.minor = MISC_DYNAMIC_MINOR; disp_misc_dev.name = "mtk_disp"; disp_misc_dev.fops = &disp_fops; disp_misc_dev.parent = NULL; ret = misc_register(&disp_misc_dev); if (ret) { pr_err("disp: fail to create mtk_disp node\n"); return ERR_PTR(ret); } // secure video path implementation: a physical address is allocated to place a handle for decryption buffer. init_tplay_handle(&(pdev->dev)); // non-zero value for valid VA #endif new_count = nr_dispsys_dev + 1; dispsys_dev = krealloc(dispsys_dev, sizeof(struct dispsys_device) * new_count, GFP_KERNEL); if (!dispsys_dev) { DDPERR("Unable to allocate dispsys_dev\n"); return -ENOMEM; } dispsys_dev = &(dispsys_dev[nr_dispsys_dev]); dispsys_dev->dev = &pdev->dev; /* iomap registers and irq*/ for(i=0;i<DISP_REG_NUM;i++) { dispsys_dev->regs[i] = of_iomap(pdev->dev.of_node, i); if (!dispsys_dev->regs[i]) { continue; // skip } dispsys_reg[i] = dispsys_dev->regs[i]; /* get IRQ ID and request IRQ */ dispsys_dev->irq[i] = irq_of_parse_and_map(pdev->dev.of_node, i); dispsys_irq[i] = dispsys_dev->irq[i]; if (!dispsys_dev->irq[i]) { continue; // skip } if(disp_is_intr_enable(i)==1) { ret = request_irq(dispsys_dev->irq[i], (irq_handler_t)disp_irq_handler, IRQF_TRIGGER_NONE, DISP_DEVNAME, NULL); // IRQF_TRIGGER_NONE dose not take effect here, real trigger mode set in dts file if (ret) { DDPERR("Unable to request IRQ, request_irq fail, i=%d, irq=%d \n", i, dispsys_dev->irq[i]); return ret; } } DDPMSG("DT, i=%d, module=%s, map_addr=%p, map_irq=%d, reg_pa=0x%x, irq=%d \n", i, ddp_get_reg_module_name(i), dispsys_dev->regs[i], dispsys_dev->irq[i], ddp_reg_pa_base[i], ddp_irq_num[i]); } nr_dispsys_dev = new_count; //mipi tx reg map here dsi_reg_va = dispsys_reg[DISP_REG_DSI0]; mipi_tx_reg = dispsys_reg[DISP_REG_MIPI]; DPI_REG = (PDPI_REGS)dispsys_reg[DISP_REG_DPI0]; ////// power on MMSYS for early porting #ifdef CONFIG_FPGA_EARLY_PORTING printk("[DISP Probe] power MMSYS:0x%lx,0x%lx\n",DISP_REG_CONFIG_MMSYS_CG_CLR0,DISP_REG_CONFIG_MMSYS_CG_CLR1); DISP_REG_SET(0,DISP_REG_CONFIG_MMSYS_CG_CLR0,0xFFFFFFFF); DISP_REG_SET(0,DISP_REG_CONFIG_MMSYS_CG_CLR1,0xFFFFFFFF); DISP_REG_SET(0,DISPSYS_CONFIG_BASE + 0xC00,0x0);//fpga should set this register #endif ////// #ifdef MTKFB_NO_M4U DISP_REG_SET(0,DISP_REG_SMI_LARB_MMU_EN,0x0);//m4u disable #endif // init arrays ddp_path_init(); // init M4U callback DDPMSG("register m4u callback\n"); m4u_register_fault_callback(M4U_PORT_DISP_OVL0, disp_m4u_callback, 0); m4u_register_fault_callback(M4U_PORT_DISP_RDMA0, disp_m4u_callback, 0); m4u_register_fault_callback(M4U_PORT_DISP_WDMA0, disp_m4u_callback, 0); #if defined(MTK_FB_OVL1_SUPPORT) m4u_register_fault_callback(M4U_PORT_DISP_OVL1, disp_m4u_callback, 0); #endif #if defined(MTK_FB_RDMA1_SUPPORT) m4u_register_fault_callback(M4U_PORT_DISP_RDMA1, disp_m4u_callback, 0); #endif DDPMSG("dispsys probe done.\n"); //NOT_REFERENCED(class_dev); // bus hang issue error intr enable // when MMSYS clock off but GPU/MJC/PWM clock on, avoid display hang and trigger error intr { DISP_REG_SET_FIELD(0, MMSYS_TO_MFG_TX_ERROR, DISP_REG_CONFIG_MMSYS_INTEN, 1); DISP_REG_SET_FIELD(0, MMSYS_TO_MJC_TX_ERROR, DISP_REG_CONFIG_MMSYS_INTEN, 1); DISP_REG_SET_FIELD(0, PWM0_APB_TX_ERROR, DISP_REG_CONFIG_MMSYS_INTEN, 1); } /* sysfs */ DDPMSG("sysfs disp +"); //add kobject if(kobject_init_and_add(&kdispobj, &disp_kobj_ktype, NULL, "disp") <0){ DDPERR("fail to add disp\n"); return -ENOMEM; } return 0; }
static void disp_debug_api(unsigned int enable, char *buf) { if (enable == 1) { DDPMSG("[DDP] debug=1, trigger AEE\n"); /* aee_kernel_exception("DDP-TEST-ASSERT", "[DDP] DDP-TEST-ASSERT"); */ } else if (enable == 2) { ddp_mem_test(); } else if (enable == 3) { ddp_lcd_test(); } else if (enable == 4) { DDPAEE("test enable=%d\n", enable); sprintf(buf, "test enable=%d\n", enable); } else if (enable == 5) { if (gDDPError == 0) gDDPError = 1; else gDDPError = 0; sprintf(buf, "bypass PQ: %d\n", gDDPError); DDPMSG("bypass PQ: %d\n", gDDPError); } else if (enable == 6) { /*ddp_dump_analysis(DISP_MODULE_DSI0);*/ ddp_dump_reg(DISP_MODULE_DSI0); } else if (enable == 7) { if (dbg_log_level < 3) dbg_log_level++; else dbg_log_level = 0; pr_debug("DDP: dbg_log_level=%d\n", dbg_log_level); sprintf(buf, "dbg_log_level: %d\n", dbg_log_level); } else if (enable == 8) { DDPDUMP("clock_mm setting:%u\n", DISP_REG_GET(DISP_REG_CONFIG_C11)); if (DISP_REG_GET(DISP_REG_CONFIG_C11) & 0xff000000 != 0xff000000) { DDPDUMP ("error, MM clock bit 24~bit31 should be 1, but real value=0x%x", DISP_REG_GET(DISP_REG_CONFIG_C11)); } } else if (enable == 9) { gOVLBackground = 0xFF0000FF; pr_debug("DDP: gOVLBackground=%d\n", gOVLBackground); sprintf(buf, "gOVLBackground: %d\n", gOVLBackground); } else if (enable == 10) { gOVLBackground = 0xFF000000; pr_debug("DDP: gOVLBackground=%d\n", gOVLBackground); sprintf(buf, "gOVLBackground: %d\n", gOVLBackground); } else if (enable == 11) { dispsys_irq[DISP_REG_NUM]; ddp_irq_num[DISP_REG_NUM]; unsigned int i = 0; char *buf_temp = buf; for (i = 0; i < DISP_REG_NUM; i++) { DDPDUMP ("i=%d, module=%s, va=0x%lx, pa=0x%x, irq(%d,%d)\n", i, ddp_get_reg_module_name(i), dispsys_reg[i], ddp_reg_pa_base[i], dispsys_irq[i], ddp_irq_num[i]); sprintf(buf_temp, "i=%d, module=%s, va=0x%lx, pa=0x%x, irq(%d,%d)\n", i, ddp_get_reg_module_name(i), dispsys_reg[i], ddp_reg_pa_base[i], dispsys_irq[i], ddp_irq_num[i]); buf_temp += strlen(buf_temp); } } else if (enable == 12) { if (gUltraEnable == 0) gUltraEnable = 1; else gUltraEnable = 0; pr_debug("DDP : gUltraEnable = %d\n", gUltraEnable); sprintf(buf, "gUltraEnable: %d\n", gUltraEnable); } else if (enable == 13) { /*int ovl_status = ovl_get_status(); config.type = DISP_SESSION_MEMORY; config.device_id = 0; disp_create_session(&config); pr_debug("old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status()); sprintf(buf, "old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status()); */ } else if (enable == 14) { /*int ovl_status = ovl_get_status(); disp_destroy_session(&config); pr_debug("old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status()); sprintf(buf, "old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status()); */ } else if (enable == 15) { /* extern smi_dumpDebugMsg(void); */ ddp_dump_analysis(DISP_MODULE_CONFIG); ddp_dump_analysis(DISP_MODULE_RDMA0); ddp_dump_analysis(DISP_MODULE_OVL0); ddp_dump_analysis(DISP_MODULE_OVL1); /* dump ultra/preultra related regs */ DDPMSG("wdma_con1(2c) = 0x%x, wdma_con2(0x38) = 0x%x, rdma_gmc0(30) = 0x%x", DISP_REG_GET(DISP_REG_WDMA_BUF_CON1), DISP_REG_GET(DISP_REG_WDMA_BUF_CON2), DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_0)); DDPMSG(" rdma_gmc1(38) = 0x%x, fifo_con(40) = 0x%x\n ", DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_1), DISP_REG_GET(DISP_REG_RDMA_FIFO_CON)); DDPMSG(" ovl0_gmc : 0x%x, 0x%x, 0x%x, 0x%x, ovl1_gmc : 0x%x, 0x%x, 0x%x, 0x%x\n ", DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING), DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING), DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING), DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING), DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING + DISP_OVL_INDEX_OFFSET), DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING + DISP_OVL_INDEX_OFFSET), DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING + DISP_OVL_INDEX_OFFSET), DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING + DISP_OVL_INDEX_OFFSET)); /* dump smi regs */ /* smi_dumpDebugMsg(); */ } else if (enable == 16) { if (gDumpMemoutCmdq == 0) gDumpMemoutCmdq = 1; else gDumpMemoutCmdq = 0; pr_debug(" DDP : gDumpMemoutCmdq = %d\n ", gDumpMemoutCmdq); sprintf(buf, " gDumpMemoutCmdq : %d\n ", gDumpMemoutCmdq); } else if (enable == 21) { if (gEnableSODIControl == 0) gEnableSODIControl = 1; else gEnableSODIControl = 0; pr_debug(" DDP : gEnableSODIControl = %d\n ", gEnableSODIControl); sprintf(buf, " gEnableSODIControl : %d\n ", gEnableSODIControl); } else if (enable == 22) { if (gPrefetchControl == 0) gPrefetchControl = 1; else gPrefetchControl = 0; pr_debug(" DDP : gPrefetchControl = %d\n ", gPrefetchControl); sprintf(buf, " gPrefetchControl : %d\n ", gPrefetchControl); } else if (enable == 23) { if (disp_low_power_enlarge_blanking == 0) disp_low_power_enlarge_blanking = 1; else disp_low_power_enlarge_blanking = 0; pr_debug(" DDP : disp_low_power_enlarge_blanking = %d\n ", disp_low_power_enlarge_blanking); sprintf(buf, " disp_low_power_enlarge_blanking : %d\n ", disp_low_power_enlarge_blanking); } else if (enable == 24) { if (disp_low_power_disable_ddp_clock == 0) disp_low_power_disable_ddp_clock = 1; else disp_low_power_disable_ddp_clock = 0; pr_debug(" DDP : disp_low_power_disable_ddp_clock = %d\n ", disp_low_power_disable_ddp_clock); sprintf(buf, " disp_low_power_disable_ddp_clock : %d\n ", disp_low_power_disable_ddp_clock); } else if (enable == 25) { if (disp_low_power_disable_fence_thread == 0) disp_low_power_disable_fence_thread = 1; else disp_low_power_disable_fence_thread = 0; pr_debug(" DDP : disp_low_power_disable_fence_thread = %d\n ", disp_low_power_disable_fence_thread); sprintf(buf, " disp_low_power_disable_fence_thread : %d\n ", disp_low_power_disable_fence_thread); } else if (enable == 26) { if (disp_low_power_remove_ovl == 0) disp_low_power_remove_ovl = 1; else disp_low_power_remove_ovl = 0; pr_debug(" DDP : disp_low_power_remove_ovl = %d\n ", disp_low_power_remove_ovl); sprintf(buf, " disp_low_power_remove_ovl : %d\n ", disp_low_power_remove_ovl); } else if (enable == 27) { if (gSkipIdleDetect == 0) gSkipIdleDetect = 1; else gSkipIdleDetect = 0; pr_debug(" DDP : gSkipIdleDetect = %d\n ", gSkipIdleDetect); sprintf(buf, " gSkipIdleDetect : %d\n ", gSkipIdleDetect); } else if (enable == 28) { if (gDumpClockStatus == 0) gDumpClockStatus = 1; else gDumpClockStatus = 0; pr_debug(" DDP : gDumpClockStatus = %d\n ", gDumpClockStatus); sprintf(buf, " gDumpClockStatus : %d\n ", gDumpClockStatus); } else if (enable == 29) { if (gEnableUartLog == 0) gEnableUartLog = 1; else gEnableUartLog = 0; pr_debug(" DDP : gEnableUartLog = %d\n ", gEnableUartLog); sprintf(buf, " gEnableUartLog : %d\n ", gEnableUartLog); } else if (enable == 30) { if (gEnableMutexRisingEdge == 0) { gEnableMutexRisingEdge = 1; DISP_REG_SET_FIELD(0, SOF_FLD_MUTEX0_SOF_TIMING, DISP_REG_CONFIG_MUTEX0_SOF, 1); } else { gEnableMutexRisingEdge = 0; DISP_REG_SET_FIELD(0, SOF_FLD_MUTEX0_SOF_TIMING, DISP_REG_CONFIG_MUTEX0_SOF, 0); } pr_debug(" DDP : gEnableMutexRisingEdge = %d\n ", gEnableMutexRisingEdge); sprintf(buf, " gEnableMutexRisingEdge : %d\n ", gEnableMutexRisingEdge); } else if (enable == 31) { if (gEnableReduceRegWrite == 0) gEnableReduceRegWrite = 1; else gEnableReduceRegWrite = 0; pr_debug(" DDP : gEnableReduceRegWrite = %d\n ", gEnableReduceRegWrite); sprintf(buf, " gEnableReduceRegWrite : %d\n ", gEnableReduceRegWrite); } else if (enable == 32) { /* DDPAEE(" DDP : (32) gEnableReduceRegWrite = %d\n ", gEnableReduceRegWrite); */ } else if (enable == 33) { if (gDumpConfigCMD == 0) gDumpConfigCMD = 1; else gDumpConfigCMD = 0; pr_debug(" DDP : gDumpConfigCMD = %d\n ", gDumpConfigCMD); sprintf(buf, " gDumpConfigCMD : %d\n ", gDumpConfigCMD); } else if (enable == 34) { if (gESDEnableSODI == 0) gESDEnableSODI = 1; else gESDEnableSODI = 0; pr_debug(" DDP : gESDEnableSODI = %d\n ", gESDEnableSODI); sprintf(buf, " gESDEnableSODI : %d\n ", gESDEnableSODI); } else if (enable == 35) { if (gEnableOVLStatusCheck == 0) gEnableOVLStatusCheck = 1; else gEnableOVLStatusCheck = 0; pr_debug(" DDP : gEnableOVLStatusCheck = %d\n ", gEnableOVLStatusCheck); sprintf(buf, " gEnableOVLStatusCheck : %d\n ", gEnableOVLStatusCheck); } else if (enable == 36) { if (gResetRDMAEnable == 0) gResetRDMAEnable = 1; else gResetRDMAEnable = 0; pr_debug(" DDP : gResetRDMAEnable = %d\n ", gResetRDMAEnable); sprintf(buf, " gResetRDMAEnable : %d\n ", gResetRDMAEnable); } else if (enable == 37) { unsigned int reg_value = 0; if (gEnableIRQ == 0) { gEnableIRQ = 1; /* OVL0/OVL1 */ DISP_CPU_REG_SET(DISP_REG_OVL_INTEN, 0x1e2); DISP_CPU_REG_SET(DISP_REG_OVL_INTEN + DISP_OVL_INDEX_OFFSET, 0x1e2); /* Mutex0 */ reg_value = DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTEN); DISP_CPU_REG_SET(DISP_REG_CONFIG_MUTEX_INTEN, reg_value | (1 << 0) | (1 << DISP_MUTEX_TOTAL)); /* RDMA0 */ DISP_CPU_REG_SET(DISP_REG_RDMA_INT_ENABLE, 0x3E); } else { gEnableIRQ = 0; /* OVL0/OVL1 */ DISP_CPU_REG_SET(DISP_REG_OVL_INTEN, 0x1e0); DISP_CPU_REG_SET(DISP_REG_OVL_INTEN + DISP_OVL_INDEX_OFFSET, 0x1e0); /* Mutex0 */ reg_value = DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTEN); DISP_CPU_REG_SET(DISP_REG_CONFIG_MUTEX_INTEN, reg_value & (~(1 << 0)) & (~(1 << DISP_MUTEX_TOTAL))); /* RDMA0 */ DISP_CPU_REG_SET(DISP_REG_RDMA_INT_ENABLE, 0x18); } pr_debug(" DDP : gEnableIRQ = %d\n ", gEnableIRQ); sprintf(buf, " gEnableIRQ : %d\n ", gEnableIRQ); } else if (enable == 38) { if (gDisableSODIForTriggerLoop == 0) gDisableSODIForTriggerLoop = 1; else gDisableSODIForTriggerLoop = 0; pr_debug(" DDP : gDisableSODIForTriggerLoop = %d\n ", gDisableSODIForTriggerLoop); sprintf(buf, " gDisableSODIForTriggerLoop : %d\n ", gDisableSODIForTriggerLoop); } else if (enable == 39) { cmdqCoreSetEvent(CMDQ_SYNC_TOKEN_STREAM_EOF); cmdqCoreSetEvent(CMDQ_EVENT_DISP_RDMA0_EOF); sprintf(buf, " enable = %d\n ", enable); } else if (enable == 41) { if (gResetOVLInAALTrigger == 0) gResetOVLInAALTrigger = 1; else gResetOVLInAALTrigger = 0; pr_debug(" DDP : gResetOVLInAALTrigger = %d\n ", gResetOVLInAALTrigger); sprintf(buf, " gResetOVLInAALTrigger : %d\n ", gResetOVLInAALTrigger); } else if (enable == 42) { if (gDisableOVLTF == 0) gDisableOVLTF = 1; else gDisableOVLTF = 0; pr_debug(" DDP : gDisableOVLTF = %d\n ", gDisableOVLTF); sprintf(buf, " gDisableOVLTF : %d\n ", gDisableOVLTF); } else if (enable == 43) { if (gDumpESDCMD == 0) gDumpESDCMD = 1; else gDumpESDCMD = 0; pr_debug(" DDP : gDumpESDCMD = %d\n ", gDumpESDCMD); sprintf(buf, " gDumpESDCMD : %d\n ", gDumpESDCMD); } else if (enable == 44) { disp_dump_emi_status(); disp_dump_emi_status(); sprintf(buf, " dump emi status !\n "); } else if (enable == 45) { if (gEnableCMDQProfile == 0) gEnableCMDQProfile = 1; else gEnableCMDQProfile = 0; pr_debug(" DDP : gEnableCMDQProfile = %d\n ", gEnableCMDQProfile); sprintf(buf, " gEnableCMDQProfile : %d\n ", gEnableCMDQProfile); } else if (enable == 46) { disp_set_pll(156); pr_debug(" DDP : disp_set_pll = 156.\n "); sprintf(buf, " disp_set_pll = 156.\n "); } else if (enable == 47) { disp_set_pll(182); pr_debug(" DDP : disp_set_pll = 182.\n "); sprintf(buf, " disp_set_pll = 182.\n "); } else if (enable == 48) { disp_set_pll(364); pr_debug(" DDP : disp_set_pll = 364\n "); sprintf(buf, " disp_set_pll = 364.\n "); } else if (enable == 49) { if (gChangeRDMAThreshold == 0) gChangeRDMAThreshold = 1; else gChangeRDMAThreshold = 0; pr_debug(" DDP : gChangeRDMAThreshold = %d\n ", gChangeRDMAThreshold); sprintf(buf, " gChangeRDMAThreshold : %d\n ", gChangeRDMAThreshold); } else if (enable == 50) { if (gChangeMMClock == 0) gChangeMMClock = 1; else gChangeMMClock = 0; pr_debug(" DDP : gChangeMMClock = %d\n ", gChangeMMClock); sprintf(buf, " gChangeMMClock : %d\n ", gChangeMMClock); } else if (enable == 51) { if (gEnableUnderflowAEE == 0) gEnableUnderflowAEE = 1; else gEnableUnderflowAEE = 0; pr_debug(" DDP : gEnableUnderflowAEE = %d\n ", gEnableUnderflowAEE); sprintf(buf, " gEnableUnderflowAEE : %d\n ", gEnableUnderflowAEE); } else if (enable == 52) { unsigned int time; cmdqRecHandle handle = NULL; cmdqRecCreate(CMDQ_SCENARIO_PRIMARY_DISP, &handle); time = disp_set_pll_by_cmdq(156, handle); pr_debug(" DDP : disp_set_pll_by_cmdq = 156. estimate execute time = %d\n ", time); sprintf(buf, " disp_set_pll_by_cmdq = 156. estimate execute time = %d\n ", time); cmdqRecDestroy(handle); } else if (enable == 53) { unsigned int time; cmdqRecHandle handle = NULL; cmdqRecCreate(CMDQ_SCENARIO_PRIMARY_DISP, &handle); time = disp_set_pll_by_cmdq(182, handle); pr_debug(" DDP : disp_set_pll_by_cmdq = 182. estimate execute time = %d\n ", time); sprintf(buf, " disp_set_pll_by_cmdq = 182. estimate execute time = %d\n ", time); cmdqRecDestroy(handle); } else if (enable == 54) { unsigned int time; cmdqRecHandle handle = NULL; cmdqRecCreate(CMDQ_SCENARIO_PRIMARY_DISP, &handle); time = disp_set_pll_by_cmdq(364, handle); pr_debug(" DDP : disp_set_pll_by_cmdq = 364. estimate execute time = %d\n ", time); sprintf(buf, " disp_set_pll_by_cmdq = 364. estimate execute time = %d\n ", time); cmdqRecDestroy(handle); } else if (enable == 55) { if (gIssueRequestThreshold == 0) gIssueRequestThreshold = 1; else gIssueRequestThreshold = 0; pr_debug(" DDP : gIssueRequestThreshold = %d\n ", gIssueRequestThreshold); sprintf(buf, " gIssueRequestThreshold : %d\n ", gIssueRequestThreshold); } else if (enable == 56) { if (gDisableIRQWhenIdle == 0) gDisableIRQWhenIdle = 1; else gDisableIRQWhenIdle = 0; pr_debug(" DDP : gDisableIRQWhenIdle = %d\n ", gDisableIRQWhenIdle); sprintf(buf, " gDisableIRQWhenIdle : %d\n ", gDisableIRQWhenIdle); } else if (enable == 57) { if (gEnableSODIWhenIdle == 0) gEnableSODIWhenIdle = 1; else gEnableSODIWhenIdle = 0; pr_debug(" DDP : gEnableSODIWhenIdle = %d\n ", gEnableSODIWhenIdle); sprintf(buf, " gEnableSODIWhenIdle : %d\n ", gEnableSODIWhenIdle); } else if (enable == 58) { #ifdef DISP_ENABLE_LAYER_FRAME if (gAddFrame == 0) gAddFrame = 1; else gAddFrame = 0; pr_debug(" DDP : gAddFrame = %d\n ", gAddFrame); sprintf(buf, " gAddFrame : %d\n ", gAddFrame); #else pr_debug(" Please enable DISP_ENABLE_LAYER_FRAME in ddp_debug.h first !\n "); sprintf(buf, " Please enable DISP_ENABLE_LAYER_FRAME in ddp_debug.h first !\n "); #endif } else if (enable == 40) { sprintf(buf, " version : %d, %s\n ", 12, __TIME__); } else if (enable==59) { extern void ddp_reset_test(void); ddp_reset_test(); sprintf(buf, " dp_reset_test called. \n "); } else if (enable == 60) { unsigned int i = 0; int *modules = ddp_get_scenario_list(DDP_SCENARIO_PRIMARY_DISP); int module_num = ddp_get_module_num(DDP_SCENARIO_PRIMARY_DISP); pr_debug("dump path status:"); for (i = 0; i < module_num; i++) pr_debug("%s-", ddp_get_module_name(modules[i])); pr_debug("\n"); ddp_dump_analysis(DISP_MODULE_CONFIG); ddp_dump_analysis(DISP_MODULE_MUTEX); for (i = 0; i < module_num; i++) ddp_dump_analysis(modules[i]); if (primary_display_is_decouple_mode()) { ddp_dump_analysis(DISP_MODULE_OVL0); ddp_dump_analysis(DISP_MODULE_OVL1); ddp_dump_analysis(DISP_MODULE_WDMA0); } ddp_dump_reg(DISP_MODULE_CONFIG); ddp_dump_reg(DISP_MODULE_MUTEX); if (primary_display_is_decouple_mode()) { ddp_dump_reg(DISP_MODULE_OVL0); ddp_dump_reg(DISP_MODULE_OVL1); ddp_dump_reg(DISP_MODULE_WDMA0); } for (i = 0; i < module_num; i++) ddp_dump_reg(modules[i]); } }
static int disp_probe(struct platform_device *pdev) { struct class_device; int ret; int i; int new_count; static unsigned int disp_probe_cnt = 0; if(disp_probe_cnt!=0) { return 0; } new_count = nr_dispsys_dev + 1; dispsys_dev = krealloc(dispsys_dev, sizeof(struct dispsys_device) * new_count, GFP_KERNEL); if (!dispsys_dev) { DDPERR("Unable to allocate dispsys_dev\n"); return -ENOMEM; } dispsys_dev = &(dispsys_dev[nr_dispsys_dev]); dispsys_dev->dev = &pdev->dev; /* iomap registers and irq*/ for(i=0;i<DISP_REG_NUM;i++) { struct resource res; dispsys_dev->regs[i] = of_iomap(pdev->dev.of_node, i); if (!dispsys_dev->regs[i]) { DDPERR("Unable to ioremap registers, of_iomap fail, i=%d \n", i); return -ENOMEM; } dispsys_reg[i] = dispsys_dev->regs[i]; /* check physical register */ of_address_to_resource(pdev->dev.of_node, i, &res); if(ddp_reg_pa_base[i] != res.start) DDPERR("DT err, i=%d, module=%s, map_addr=%p, reg_pa=0x%x!=0x%pa\n", i, ddp_get_reg_module_name(i), dispsys_dev->regs[i], ddp_reg_pa_base[i], &res.start); /* get IRQ ID and request IRQ */ { dispsys_dev->irq[i] = irq_of_parse_and_map(pdev->dev.of_node, i); dispsys_irq[i] = dispsys_dev->irq[i]; if(disp_is_intr_enable(i)==1) { ret = request_irq(dispsys_dev->irq[i], (irq_handler_t)disp_irq_handler, IRQF_TRIGGER_NONE, ddp_get_reg_module_name(i), NULL); // IRQF_TRIGGER_NONE dose not take effect here, real trigger mode set in dts file if (ret) { DDPERR("Unable to request IRQ, request_irq fail, i=%d, irq=%d \n", i, dispsys_dev->irq[i]); return ret; } DDPMSG("irq enabled, module=%s, irq=%d \n", ddp_get_reg_module_name(i), dispsys_dev->irq[i]); } } DDPMSG("DT, i=%d, module=%s, map_addr=%p, map_irq=%d, reg_pa=0x%x\n", i, ddp_get_reg_module_name(i), dispsys_dev->regs[i], dispsys_dev->irq[i], ddp_reg_pa_base[i]); } nr_dispsys_dev = new_count; //mipi tx reg map here ////// power on MMSYS for early porting #ifdef CONFIG_FPGA_EARLY_PORTING printk("[DISP Probe] power MMSYS:0x%lx,0x%lx\n",DISP_REG_CONFIG_MMSYS_CG_CLR0,DISP_REG_CONFIG_MMSYS_CG_CLR1); DISP_REG_SET(0,DISP_REG_CONFIG_MMSYS_CG_CLR0,0xFFFFFFFF); DISP_REG_SET(0,DISP_REG_CONFIG_MMSYS_CG_CLR1,0xFFFFFFFF); DISP_REG_SET(0,DISPSYS_CONFIG_BASE + 0xC04,0x1C000);//fpga should set this register #endif ////// // init arrays ddp_path_init(); // init M4U callback #ifdef early_porting_by_k DDPMSG("register m4u callback\n"); m4u_register_fault_callback(M4U_PORT_DISP_OVL0, disp_m4u_callback, 0); m4u_register_fault_callback(M4U_PORT_DISP_RDMA0, disp_m4u_callback, 0); m4u_register_fault_callback(M4U_PORT_DISP_WDMA0, disp_m4u_callback, 0); m4u_register_fault_callback(M4U_PORT_DISP_OVL1, disp_m4u_callback, 0); m4u_register_fault_callback(M4U_PORT_DISP_RDMA1, disp_m4u_callback, 0); m4u_register_fault_callback(M4U_PORT_DISP_WDMA1, disp_m4u_callback, 0); #endif DDPMSG("dispsys probe done.\n"); //NOT_REFERENCED(class_dev); return 0; }
static void process_dbg_debug(const char *opt) { unsigned int enable = 0; static disp_session_config config; char *p; char *buf = dbg_buf + strlen(dbg_buf); int ret; p = (char *)opt + 6; ret = kstrtoul(p, 10, (long unsigned int *)&enable); if (ret) pr_err("DISP/%s: errno %d\n", __func__, ret); if (enable == 1) { DDPMSG("[DDP] debug=1, trigger AEE\n"); /* aee_kernel_exception("DDP-TEST-ASSERT", "[DDP] DDP-TEST-ASSERT"); */ } else if (enable == 2) { ddp_mem_test(); } else if (enable == 3) { ddp_lcd_test(); } else if (enable == 4) { DDPAEE("test enable=%d\n", enable); sprintf(buf, "test enable=%d\n", enable); } else if (enable == 5) { if (gDDPError == 0) gDDPError = 1; else gDDPError = 0; sprintf(buf, "bypass PQ: %d\n", gDDPError); DDPMSG("bypass PQ: %d\n", gDDPError); } else if (enable == 6) { unsigned int i = 0; int *modules = ddp_get_scenario_list(DDP_SCENARIO_PRIMARY_DISP); int module_num = ddp_get_module_num(DDP_SCENARIO_PRIMARY_DISP); pr_debug("dump path status:"); for (i = 0; i < module_num; i++) pr_debug("%s-", ddp_get_module_name(modules[i])); pr_debug("\n"); ddp_dump_analysis(DISP_MODULE_CONFIG); ddp_dump_analysis(DISP_MODULE_MUTEX); for (i = 0; i < module_num; i++) ddp_dump_analysis(modules[i]); if (primary_display_is_decouple_mode()) { ddp_dump_analysis(DISP_MODULE_OVL0); #if defined(OVL_CASCADE_SUPPORT) ddp_dump_analysis(DISP_MODULE_OVL1); #endif ddp_dump_analysis(DISP_MODULE_WDMA0); } ddp_dump_reg(DISP_MODULE_CONFIG); ddp_dump_reg(DISP_MODULE_MUTEX); if (primary_display_is_decouple_mode()) { ddp_dump_reg(DISP_MODULE_OVL0); ddp_dump_reg(DISP_MODULE_OVL1); ddp_dump_reg(DISP_MODULE_WDMA0); } for (i = 0; i < module_num; i++) ddp_dump_reg(modules[i]); } else if (enable == 7) { if (dbg_log_level < 3) dbg_log_level++; else dbg_log_level = 0; pr_debug("DDP: dbg_log_level=%d\n", dbg_log_level); sprintf(buf, "dbg_log_level: %d\n", dbg_log_level); } else if (enable == 8) { DDPDUMP("clock_mm setting:%u\n", DISP_REG_GET(DISP_REG_CONFIG_C11)); if ((DISP_REG_GET(DISP_REG_CONFIG_C11) & 0xff000000) != 0xff000000) DDPDUMP("error, MM clock bit 24~bit31 should be 1, but real value=0x%x", DISP_REG_GET(DISP_REG_CONFIG_C11)); } else if (enable == 9) { gOVLBackground = 0xFF0000FF; pr_debug("DDP: gOVLBackground=%d\n", gOVLBackground); sprintf(buf, "gOVLBackground: %d\n", gOVLBackground); } else if (enable == 10) { gOVLBackground = 0xFF000000; pr_debug("DDP: gOVLBackground=%d\n", gOVLBackground); sprintf(buf, "gOVLBackground: %d\n", gOVLBackground); } else if (enable == 11) { unsigned int i = 0; char *buf_temp = buf; for (i = 0; i < DISP_REG_NUM; i++) { DDPDUMP("i=%d, module=%s, va=0x%lx, pa=0x%x, irq(%d,%d)\n", i, ddp_get_reg_module_name(i), dispsys_reg[i], ddp_reg_pa_base[i], dispsys_irq[i], ddp_irq_num[i]); sprintf(buf_temp, "i=%d, module=%s, va=0x%lx, pa=0x%x, irq(%d,%d)\n", i, ddp_get_reg_module_name(i), dispsys_reg[i], ddp_reg_pa_base[i], dispsys_irq[i], ddp_irq_num[i]); buf_temp += strlen(buf_temp); } } else if (enable == 12) { if (gUltraEnable == 0) gUltraEnable = 1; else gUltraEnable = 0; pr_debug("DDP: gUltraEnable=%d\n", gUltraEnable); sprintf(buf, "gUltraEnable: %d\n", gUltraEnable); } else if (enable == 13) { int ovl_status = ovl_get_status(); config.type = DISP_SESSION_MEMORY; config.device_id = 0; disp_create_session(&config); pr_debug("old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status()); sprintf(buf, "old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status()); } else if (enable == 14) { int ovl_status = ovl_get_status(); disp_destroy_session(&config); pr_debug("old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status()); sprintf(buf, "old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status()); } else if (enable == 15) { /* extern smi_dumpDebugMsg(void); */ ddp_dump_analysis(DISP_MODULE_CONFIG); ddp_dump_analysis(DISP_MODULE_RDMA0); ddp_dump_analysis(DISP_MODULE_OVL0); #if defined(OVL_CASCADE_SUPPORT) ddp_dump_analysis(DISP_MODULE_OVL1); #endif /* dump ultra/preultra related regs */ DDPMSG("wdma_con1(2c)=0x%x, wdma_con2(0x38)=0x%x,\n", DISP_REG_GET(DISP_REG_WDMA_BUF_CON1), DISP_REG_GET(DISP_REG_WDMA_BUF_CON2)); DDPMSG("rdma_gmc0(30)=0x%x, rdma_gmc1(38)=0x%x, fifo_con(40)=0x%x\n", DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_0), DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_1), DISP_REG_GET(DISP_REG_RDMA_FIFO_CON)); DDPMSG("ovl0_gmc: 0x%x, 0x%x, 0x%x, 0x%x, ovl1_gmc: 0x%x, 0x%x, 0x%x, 0x%x,\n", DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING), DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING), DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING), DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING), DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING + DISP_OVL_INDEX_OFFSET), DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING + DISP_OVL_INDEX_OFFSET), DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING + DISP_OVL_INDEX_OFFSET), DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING + DISP_OVL_INDEX_OFFSET)); /* dump smi regs */ /* smi_dumpDebugMsg(); */ } else if (enable == 16) { if (gDumpMemoutCmdq == 0) gDumpMemoutCmdq = 1; else gDumpMemoutCmdq = 0; pr_debug("DDP: gDumpMemoutCmdq=%d\n", gDumpMemoutCmdq); sprintf(buf, "gDumpMemoutCmdq: %d\n", gDumpMemoutCmdq); } else if (enable == 21) { if (gEnableSODIControl == 0) gEnableSODIControl = 1; else gEnableSODIControl = 0; pr_debug("DDP: gEnableSODIControl=%d\n", gEnableSODIControl); sprintf(buf, "gEnableSODIControl: %d\n", gEnableSODIControl); } else if (enable == 22) { if (gPrefetchControl == 0) gPrefetchControl = 1; else gPrefetchControl = 0; pr_debug("DDP: gPrefetchControl=%d\n", gPrefetchControl); sprintf(buf, "gPrefetchControl: %d\n", gPrefetchControl); } else if (enable == 23) { if (disp_low_power_enlarge_blanking == 0) disp_low_power_enlarge_blanking = 1; else disp_low_power_enlarge_blanking = 0; pr_debug("DDP: disp_low_power_enlarge_blanking=%d\n", disp_low_power_enlarge_blanking); sprintf(buf, "disp_low_power_enlarge_blanking: %d\n", disp_low_power_enlarge_blanking); } else if (enable == 24) { if (disp_low_power_disable_ddp_clock == 0) disp_low_power_disable_ddp_clock = 1; else disp_low_power_disable_ddp_clock = 0; pr_debug("DDP: disp_low_power_disable_ddp_clock=%d\n", disp_low_power_disable_ddp_clock); sprintf(buf, "disp_low_power_disable_ddp_clock: %d\n", disp_low_power_disable_ddp_clock); } else if (enable == 25) { if (disp_low_power_disable_fence_thread == 0) disp_low_power_disable_fence_thread = 1; else disp_low_power_disable_fence_thread = 0; pr_debug("DDP: disp_low_power_disable_fence_thread=%d\n", disp_low_power_disable_fence_thread); sprintf(buf, "disp_low_power_disable_fence_thread: %d\n", disp_low_power_disable_fence_thread); } else if (enable == 26) { if (disp_low_power_remove_ovl == 0) disp_low_power_remove_ovl = 1; else disp_low_power_remove_ovl = 0; pr_debug("DDP: disp_low_power_remove_ovl=%d\n", disp_low_power_remove_ovl); sprintf(buf, "disp_low_power_remove_ovl: %d\n", disp_low_power_remove_ovl); } else if (enable == 27) { if (gSkipIdleDetect == 0) gSkipIdleDetect = 1; else gSkipIdleDetect = 0; pr_debug("DDP: gSkipIdleDetect=%d\n", gSkipIdleDetect); sprintf(buf, "gSkipIdleDetect: %d\n", gSkipIdleDetect); } else if (enable == 28) { if (gDumpClockStatus == 0) gDumpClockStatus = 1; else gDumpClockStatus = 0; pr_debug("DDP: gDumpClockStatus=%d\n", gDumpClockStatus); sprintf(buf, "gDumpClockStatus: %d\n", gDumpClockStatus); } else if (enable == 29) { if (gEnableUartLog == 0) gEnableUartLog = 1; else gEnableUartLog = 0; pr_debug("DDP: gEnableUartLog=%d\n", gEnableUartLog); sprintf(buf, "gEnableUartLog: %d\n", gEnableUartLog); } else if (enable == 30) { if (gEnableMutexRisingEdge == 0) { gEnableMutexRisingEdge = 1; DISP_REG_SET_FIELD(0, SOF_FLD_MUTEX0_SOF_TIMING, DISP_REG_CONFIG_MUTEX0_SOF, 1); } else { gEnableMutexRisingEdge = 0; DISP_REG_SET_FIELD(0, SOF_FLD_MUTEX0_SOF_TIMING, DISP_REG_CONFIG_MUTEX0_SOF, 0); } pr_debug("DDP: gEnableMutexRisingEdge=%d\n", gEnableMutexRisingEdge); sprintf(buf, "gEnableMutexRisingEdge: %d\n", gEnableMutexRisingEdge); } else if (enable == 31) { if (gEnableReduceRegWrite == 0) gEnableReduceRegWrite = 1; else gEnableReduceRegWrite = 0; pr_debug("DDP: gEnableReduceRegWrite=%d\n", gEnableReduceRegWrite); sprintf(buf, "gEnableReduceRegWrite: %d\n", gEnableReduceRegWrite); } else if (enable == 32) { DDPAEE("DDP: (32)gEnableReduceRegWrite=%d\n", gEnableReduceRegWrite); } else if (enable == 33) { if (gDumpConfigCMD == 0) gDumpConfigCMD = 1; else gDumpConfigCMD = 0; pr_debug("DDP: gDumpConfigCMD=%d\n", gDumpConfigCMD); sprintf(buf, "gDumpConfigCMD: %d\n", gDumpConfigCMD); } else if (enable == 34) { if (gESDEnableSODI == 0) gESDEnableSODI = 1; else gESDEnableSODI = 0; pr_debug("DDP: gESDEnableSODI=%d\n", gESDEnableSODI); sprintf(buf, "gESDEnableSODI: %d\n", gESDEnableSODI); } else if (enable == 35) { if (gEnableOVLStatusCheck == 0) gEnableOVLStatusCheck = 1; else gEnableOVLStatusCheck = 0; pr_debug("DDP: gEnableOVLStatusCheck=%d\n", gEnableOVLStatusCheck); sprintf(buf, "gEnableOVLStatusCheck: %d\n", gEnableOVLStatusCheck); } else if (enable == 36) { if (gResetRDMAEnable == 0) gResetRDMAEnable = 1; else gResetRDMAEnable = 0; pr_debug("DDP: gResetRDMAEnable=%d\n", gResetRDMAEnable); sprintf(buf, "gResetRDMAEnable: %d\n", gResetRDMAEnable); } else if (enable == 37) { unsigned int reg_value = 0; if (gEnableIRQ == 0) { gEnableIRQ = 1; DISP_CPU_REG_SET(DISP_REG_OVL_INTEN, 0x1e2); DISP_CPU_REG_SET(DISP_REG_OVL_INTEN + DISP_OVL_INDEX_OFFSET, 0x1e2); reg_value = DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTEN); DISP_CPU_REG_SET(DISP_REG_CONFIG_MUTEX_INTEN, reg_value | (1 << 0) | (1 << DISP_MUTEX_TOTAL)); } else { gEnableIRQ = 0; DISP_CPU_REG_SET(DISP_REG_OVL_INTEN, 0x1e0); DISP_CPU_REG_SET(DISP_REG_OVL_INTEN + DISP_OVL_INDEX_OFFSET, 0x1e0); reg_value = DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTEN); DISP_CPU_REG_SET(DISP_REG_CONFIG_MUTEX_INTEN, reg_value & (~(1 << 0)) & (~(1 << DISP_MUTEX_TOTAL))); } pr_debug("DDP: gEnableIRQ=%d\n", gEnableIRQ); sprintf(buf, "gEnableIRQ: %d\n", gEnableIRQ); } else if (enable == 38) { if (gDisableSODIForTriggerLoop == 0) gDisableSODIForTriggerLoop = 1; else gDisableSODIForTriggerLoop = 0; pr_debug("DDP: gDisableSODIForTriggerLoop=%d\n", gDisableSODIForTriggerLoop); sprintf(buf, "gDisableSODIForTriggerLoop: %d\n", gDisableSODIForTriggerLoop); } else if (enable == 39) { cmdqCoreSetEvent(CMDQ_SYNC_TOKEN_STREAM_EOF); cmdqCoreSetEvent(CMDQ_EVENT_DISP_RDMA0_EOF); sprintf(buf, "enable=%d\n", enable); } else if (enable == 41) { if (gResetOVLInAALTrigger == 0) gResetOVLInAALTrigger = 1; else gResetOVLInAALTrigger = 0; pr_debug("DDP: gResetOVLInAALTrigger=%d\n", gResetOVLInAALTrigger); sprintf(buf, "gResetOVLInAALTrigger: %d\n", gResetOVLInAALTrigger); } else if (enable == 42) { if (gDisableOVLTF == 0) gDisableOVLTF = 1; else gDisableOVLTF = 0; pr_debug("DDP: gDisableOVLTF=%d\n", gDisableOVLTF); sprintf(buf, "gDisableOVLTF: %d\n", gDisableOVLTF); } else if (enable == 43) { if (gDumpESDCMD == 0) gDumpESDCMD = 1; else gDumpESDCMD = 0; pr_debug("DDP: gDumpESDCMD=%d\n", gDumpESDCMD); sprintf(buf, "gDumpESDCMD: %d\n", gDumpESDCMD); } else if (enable == 44) { /* extern void disp_dump_emi_status(void); */ disp_dump_emi_status(); sprintf(buf, "dump emi status!\n"); } else if (enable == 40) { sprintf(buf, "version: %d, %s\n", 7, __TIME__); } else if (enable == 45) { ddp_aee_print("DDP AEE DUMP!!\n"); } else if (enable == 46) { ASSERT(0); } else if (enable == 47) { if (gEnableDSIStateCheck == 0) gEnableDSIStateCheck = 1; else gEnableDSIStateCheck = 0; pr_debug("DDP: gEnableDSIStateCheck=%d\n", gEnableDSIStateCheck); sprintf(buf, "gEnableDSIStateCheck: %d\n", gEnableDSIStateCheck); } else if (enable == 48) { if (gMutexFreeRun == 0) gMutexFreeRun = 1; else gMutexFreeRun = 0; pr_debug("DDP: gMutexFreeRun=%d\n", gMutexFreeRun); sprintf(buf, "gMutexFreeRun: %d\n", gMutexFreeRun); } }