void lowlevel_init(void* cur,void * target)
{
int i;
//close ddr
//gpiob_8
clrbits_le32(P_PREG_GGPIO_O, 1<<16);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<16);
//gpiob_5
clrbits_le32(P_PREG_GGPIO_O, 1<<13);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<13);
//gpiob_6
//clrbits_le32(P_PREG_GGPIO_O, 1<<14);
//clrbits_le32(P_PREG_GGPIO_EN_N, 1<<14);
//Adjust 1us timer base
setbits_le32(P_PREG_GGPIO_O, 1<<5);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<5);
//vcc_12v/24v power on GPIOX_70
setbits_le32(P_PREG_GGPIO_O, 1<<6);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<6);
//backlight GPIOX_53
setbits_le32(P_PREG_FGPIO_O, 1<<21);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<21);
WRITE_CBUS_REG_BITS(PREG_CTLREG0_ADDR,CONFIG_CRYSTAL_MHZ,4,5);
/*
Select TimerE 1 us base
*/
clrsetbits_le32(P_ISA_TIMER_MUX,0x7<<8,0x1<<8);
memory_pll_init(0,NULL);
//serial_put_dword(get_timer(0));
//serial_put_dword(readl(0xc1100000+0x200b*4));
#if CONFIG_ENABLE_SPL_DEBUG_ROM
__udelay(100000);//wait for a uart input
if(serial_tstc()){
writel(0,P_WATCHDOG_TC);//disable Watchdog
debug_rom(__FILE__,__LINE__);
}
#else
__udelay(1000);//delay 1 ms , wait pll ready
#endif
#if 1
#if CONFIG_ENABLE_SPL_DEBUG_ROM
if(ddr_init_test()){
writel(0,P_WATCHDOG_TC);//disable Watchdog
debug_rom(__FILE__,__LINE__);
}
#else
do{
}while(ddr_init_test(0x6));
#endif
#endif
writel(0,P_WATCHDOG_TC);//disable Watchdog
// serial_puts("\nM2C Systemp Started\n");
}
void lowlevel_init(void* cur,void * target)
{
#if 0
if(cur != target) //r0!=r1
{
//running from spi
// take me as a spi rom boot mode
romboot_info->por_cfg = POR_INTL_SPI |
(READ_CBUS_REG(ASSIST_POR_CONFIG)&(~POR_INTL_CFG_MASK));
romboot_info->boot_id = 0;//boot from spi
/// Release pull up registers .
}
#endif
power_hold();
backlight_off();
//changed by Elvis, add uart rx pull up
//pull up LINUX_RX(B15--->GPIOE_19) reg (7422y v1.pdf)
//GPIOE_19(M1-Apps v25- 2010-07-19-BGA372_297-6.xls serach B15)
WRITE_CBUS_REG( PAD_PULL_UP_REG3, READ_CBUS_REG(PAD_PULL_UP_REG3) & ~(1<<2) ); // Meson-pull-up-down_table.xlsx ( GPIOE_19 is PAD_PULL_UP_REG3---0x203e 2bits)
//Adjust 1us timer base
WRITE_CBUS_REG_BITS(PREG_CTLREG0_ADDR,CONFIG_CRYSTAL_MHZ,4,5);
/*
Select TimerE 1 us base
*/
clrsetbits_le32(P_ISA_TIMER_MUX,0x7<<8,0x1<<8);
memory_pll_init(0,NULL);
serial_puts("\nFirmware start at: ");
serial_put_dword(get_timer(0));
#if CONFIG_ENABLE_SPL_DEBUG_ROM
__udelay(100000);//wait for a uart input
if(serial_tstc())
{
debug_rom(__FILE__,__LINE__);
}
#else
__udelay(1000);//delay 1 ms , wait pll ready
#endif
// writel((0<<22)|1000000,P_WATCHDOG_TC);//enable Watchdog
unsigned por_cfg;
#if CONFIG_ENABLE_SPL_DEBUG_ROM
if(ddr_init_test())
debug_rom(__FILE__,__LINE__);
#else
do{
}while(ddr_init_test());
#endif
serial_puts("\nFirmware started, now starting u-boot...");
}
void relocate_init(unsigned __TEXT_BASE,unsigned __TEXT_SIZE)
{
unsigned por_cfg=romboot_info->por_cfg;
unsigned boot_id=romboot_info->boot_id;
unsigned size;
int i;
unsigned * mem;
int rc=0;
size=__TEXT_SIZE;
// if(rc)
// rc=fw_init_extl(por_cfg);//INTL device BOOT FAIL
// if(rc==0)
// rc=fw_load_extl(por_cfg,__TEXT_BASE,size);
// asm volatile("wfi");
if(boot_id>1)
boot_id=0;
if(boot_id==0)
{
rc=fw_load_intl(por_cfg,__TEXT_BASE,size);
if(!rc)
return ;
rc=fw_init_extl(por_cfg);//INTL device BOOT FAIL
}
if(rc==0)
{
rc=fw_load_extl(por_cfg,__TEXT_BASE,size);
}
#if CONFIG_ENABLE_SPL_DEBUG_ROM
while(rc||serial_tstc())
{
serial_put_dword(rc);
debug_rom(__FILE__,__LINE__);
#else
while(rc)
{
#endif
if(rc)
rc=fw_init_extl(por_cfg);//INTL device BOOT FAIL
if(rc==0)
rc=fw_load_extl(por_cfg,__TEXT_BASE,size);
}
#if 0 //comment out by Elvis Yu
for(i=0;i<sizeof(__load_table)/sizeof(__load_table[0]);i++)
{
if(__load_table[i].size==0)
continue;
memcpy(__load_table[i].dest,__load_table[i].src+__TEXT_BASE,__load_table[i].size);
}
// __asm__ __volatile__("wfi");
#endif
return ;
}
unsigned main(unsigned __TEXT_BASE,unsigned __TEXT_SIZE)
{
//Adjust 1us timer base
timer_init();
serial_init(UART_CONTROL_SET(CONFIG_BAUDRATE,CONFIG_CRYSTAL_MHZ*1000000));
serial_put_dword(get_utimer(0));
AML_WATCH_DOG_DISABLE();//disable Watchdog
debug_rom(__FILE__,__LINE__);
return 0;
}
void relocate_init(unsigned __TEXT_BASE,unsigned __TEXT_SIZE)
{
unsigned por_cfg=romboot_info->por_cfg;
unsigned boot_id=romboot_info->boot_id;
unsigned size;
int i;
unsigned * mem;
int rc=0;
size=__TEXT_SIZE;
if(boot_id>1)
boot_id=0;
if(boot_id==0)
{
rc=fw_load_intl(por_cfg,__TEXT_BASE,size);
if(!rc)
return ;
rc=fw_init_extl(por_cfg);//INTL device BOOT FAIL
}
if(rc==0)
{
rc=fw_load_extl(por_cfg,__TEXT_BASE,size);
}
#if CONFIG_ENABLE_SPL_DEBUG_ROM
while(rc||serial_tstc())
{
unsigned char c;
if(serial_tstc()&&serial_getc()!='e')
break;
serial_put_dword(rc);
debug_rom(__FILE__,__LINE__);
#else
while(rc)
{
#endif
if(rc)
rc=fw_init_extl(por_cfg);//INTL device BOOT FAIL
if(rc==0)
rc=fw_load_extl(por_cfg,__TEXT_BASE,size);
}
load_ext(por_cfg,boot_id,__TEXT_BASE);
// __asm__ __volatile__("wfi");
return ;
}
void relocate_init(unsigned __TEXT_BASE,unsigned __TEXT_SIZE)
{
while(1)
debug_rom(__FILE__,__LINE__);
}
void lowlevel_init(void* cur,void * target)
{
int i;
#if 0
if(cur != target) //r0!=r1
{
//running from spi
// take me as a spi rom boot mode
romboot_info->por_cfg = POR_INTL_SPI |
(READ_CBUS_REG(ASSIST_POR_CONFIG)&(~POR_INTL_CFG_MASK));
romboot_info->boot_id = 0;//boot from spi
/// Release pull up registers .
}
#endif
//gpiob_8
clrbits_le32(P_PREG_GGPIO_O, 1<<16);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<16);
//gpiob_5
clrbits_le32(P_PREG_GGPIO_O, 1<<13);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<13);
//writel((1<<22)|100000,P_WATCHDOG_TC);//enable Watchdog 1 seconds
//Adjust 1us timer base
//clrbits_le32(P_PREG_FGPIO_O, 1<<21);
//mute
// setbits_le32(P_PREG_GGPIO_O, 1<<5);
// clrbits_le32(P_PREG_GGPIO_EN_N, 1<<5);
// //vcc_12v/24v power down GPIOX_70
// setbits_le32(P_PREG_GGPIO_O, 1<<6);
// clrbits_le32(P_PREG_GGPIO_EN_N, 1<<6);
// bl
// setbits_le32(P_PREG_FGPIO_O, 1<<21);
// clrbits_le32(P_PREG_FGPIO_EN_N, 1<<21);
//Wr(REG_LVDS_PHY_CNTL4, 0);//LVDS_MDR_PU
//clrbits_le32(P_PREG_GGPIO_O, 1<<6);
//clrbits_le32(P_PREG_GGPIO_EN_N, 1<<6);
WRITE_CBUS_REG_BITS(PREG_CTLREG0_ADDR,CONFIG_CRYSTAL_MHZ,4,5);
/*
Select TimerE 1 us base
*/
clrsetbits_le32(P_ISA_TIMER_MUX,0x7<<8,0x1<<8);
if(1)
{
writel(0,P_WATCHDOG_TC);//disable Watchdog
//while(1)
{
__udelay(50000);
}
}
memory_pll_init(0,NULL);
//serial_put_dword(get_timer(0));
//serial_put_dword(readl(0xc1100000+0x200b*4));
#if CONFIG_ENABLE_SPL_DEBUG_ROM
__udelay(100000);//wait for a uart input
if(serial_tstc()){
writel(0,P_WATCHDOG_TC);//disable Watchdog
debug_rom(__FILE__,__LINE__);
}
#else
__udelay(1000);//delay 1 ms , wait pll ready
#endif
#if 1
#if CONFIG_ENABLE_SPL_DEBUG_ROM
if(ddr_init_test()){
writel(0,P_WATCHDOG_TC);//disable Watchdog
debug_rom(__FILE__,__LINE__);
}
#else
do{
}while(ddr_init_test(0x6));
#endif
#endif
writel(0,P_WATCHDOG_TC);//disable Watchdog
//serial_puts("\nM2C (Haier TV) Systemp Started\n");
}