/// report tdm timings
///
void
tdm_report_timing(void)
{
printf("silence_period: %u\n", (unsigned)silence_period); delay_msec(1);
printf("tx_window_width: %u\n", (unsigned)tx_window_width); delay_msec(1);
printf("max_data_packet_length: %u\n", (unsigned)max_data_packet_length); delay_msec(1);
}
void overrun(void)
{
volatile unsigned char *base = (unsigned char *)0x8300;
unsigned char data_L, resend;
data_L = readRTL(CR);
writeRTL(CR, 0x21);
delay_msec(2);
writeRTL(RBCR0, 0x00);
writeRTL(RBCR1, 0x00);
if(!(data_L & 0x04))
resend = 0;
else if(data_L & 0x04)
{
data_L = readRTL(ISR);
if((data_L & 0x02) || (data_L & 0x08))
resend = 0;
else
resend = 1;
}
writeRTL(TCR, 0x02);
writeRTL(CR, 0x22);
writeRTL(BNRY, RXSTART_INIT);
writeRTL(CR, 0x62);
writeRTL(CURR, RXSTART_INIT);
writeRTL(CR, 0x22);
writeRTL(ISR, 0x10);
writeRTL(TCR, TCR_INIT);
writeRTL(ISR, 0xFF);
}
void autonomous_routine3()
{
int acceleration,
c;
long velocity = 0,
position = 0;
controller_begin_autonomous_mode();
pwm_write(LEFT_DRIVE_PORT, -50);
pwm_write(RIGHT_DRIVE_PORT, 50);
controller_submit_data(WAIT);
for (c=0; c<100; ++c)
{
read_accelerometer_axis(4, 535, 5000, &acceleration, &velocity, &position);
delay_msec(10);
}
pwm_write(LEFT_DRIVE_PORT, MOTOR_STOP);
pwm_write(RIGHT_DRIVE_PORT, MOTOR_STOP);
controller_submit_data(WAIT);
controller_end_autonomous_mode();
}
void spin1(char power, unsigned short ms)
{
pwm_write(RIGHT_DRIVE_PORT, +power);
pwm_write(LEFT_DRIVE_PORT, +power);
controller_submit_data(WAIT);
delay_msec(ms);
}
void
panic(char *fmt, ...)
{
va_list ap;
puts("\n**PANIC**");
va_start(ap, fmt);
vprintf(fmt, ap);
puts("");
EA = 1;
ES0 = 1;
delay_msec(1000);
// generate a software reset
RSTSRC |= (1 << 4);
for (;;)
;
}
void initRTL8019(void)
{
unsigned char i, rb;
volatile unsigned char *base = (unsigned char *)0x8300;
RTL8019setupPorts();
/*#define nic_write writeRTL
#define nic_read readRTL*/
/*
* Disable NIC interrupts.
*/
cbi(EIMSK, INT5);
/* if(NicReset(base))
return -1;*/
#if 0
/*
* Mask all interrupts and clear any interrupt status flag to set the
* INT pin back to low.
*/
nic_write(NIC_PG0_IMR, 0);
nic_write(NIC_PG0_ISR, 0xff);
/*
* During reset the nic loaded its initial configuration from an
* external eeprom. On the ethernut board we do not have any
* configuration eeprom, but simply tied the eeprom data line to
* high level. So we have to clear some bits in the configuration
* register. Switch to register page 3.
*/
nic_write(NIC_CR, NIC_CR_STP | NIC_CR_RD2 | NIC_CR_PS0 | NIC_CR_PS1);
/*
* The nic configuration registers are write protected unless both
* EEM bits are set to 1.
*/
nic_write(NIC_PG3_EECR, NIC_EECR_EEM0 | NIC_EECR_EEM1);
/*
* Disable sleep and power down.
*/
nic_write(NIC_PG3_CONFIG3, 0);
/*
* Network media had been set to 10Base2 by the virtual EEPROM and
* will be set now to auto detect. This will initiate a link test.
* We don't force 10BaseT, because this would disable the link test.
*/
nic_write(NIC_PG3_CONFIG2, NIC_CONFIG2_BSELB);
/*
* Reenable write protection of the nic configuration registers
* and wait for link test to complete.
*/
nic_write(NIC_PG3_EECR, 0);
/* NutSleep(WAIT500);*/
delay_msec(500);
/*
* Switch to register page 0 and set data configuration register
* to byte-wide DMA transfers, normal operation (no loopback),
* send command not executed and 8 byte fifo threshold.
*/
nic_write(NIC_CR, NIC_CR_STP | NIC_CR_RD2);
nic_write(NIC_PG0_DCR, NIC_DCR_LS | NIC_DCR_FT1);
/*
* Clear remote dma byte count register.
*/
nic_write(NIC_PG0_RBCR0, 0);
nic_write(NIC_PG0_RBCR1, 0);
/*
* Temporarily set receiver to monitor mode and transmitter to
* internal loopback mode. Incoming packets will not be stored
* in the nic ring buffer and no data will be send to the network.
*/
nic_write(NIC_PG0_RCR, NIC_RCR_MON);
nic_write(NIC_PG0_TCR, NIC_TCR_LB0);
/*
* Configure the nic's ring buffer page layout.
* NIC_PG0_BNRY: Last page read.
* NIC_PG0_PSTART: First page of receiver buffer.
* NIC_PG0_PSTOP: Last page of receiver buffer.
*/
nic_write(NIC_PG0_TPSR, NIC_FIRST_TX_PAGE);
nic_write(NIC_PG0_BNRY, NIC_STOP_PAGE - 1);
nic_write(NIC_PG0_PSTART, NIC_FIRST_RX_PAGE);
nic_write(NIC_PG0_PSTOP, NIC_STOP_PAGE);
/*
* Once again clear interrupt status register.
*/
nic_write(NIC_PG0_ISR, 0xff);
/*
* Switch to register page 1 and copy our MAC address into the nic.
* We are still in stop mode.
*/
nic_write(NIC_CR, NIC_CR_STP | NIC_CR_RD2 | NIC_CR_PS0);
for(i = 0; i < 6; i++)
nic_write(NIC_PG1_PAR0 + i, mac[i]);
/*
* Clear multicast filter bits to disable all packets.
*/
for(i = 0; i < 8; i++)
nic_write(NIC_PG1_MAR0 + i, 0);
/*
* Set current page pointer to one page after the boundary pointer.
*/
nic_write(NIC_PG1_CURR, NIC_START_PAGE + TX_PAGES);
/*
* Switch back to register page 0, remaining in stop mode.
*/
nic_write(NIC_CR, NIC_CR_STP | NIC_CR_RD2);
/*
* Take receiver out of monitor mode and enable it for accepting
* broadcasts.
*/
nic_write(NIC_PG0_RCR, NIC_RCR_AB);
/*
* Clear all interrupt status flags and enable interrupts.
*/
nic_write(NIC_PG0_ISR, 0xff);
nic_write(NIC_PG0_IMR, NIC_IMR_PRXE | NIC_IMR_PTXE | NIC_IMR_RXEE |
NIC_IMR_TXEE | NIC_IMR_OVWE);
/*
* Fire up the nic by clearing the stop bit and setting the start bit.
* To activate the local receive dma we must also take the nic out of
* the local loopback mode.
*/
nic_write(NIC_CR, NIC_CR_STA | NIC_CR_RD2);
nic_write(NIC_PG0_TCR, 0);
/* NutSleep(WAIT500);*/
delay_msec(500);
#endif /* 0 */
NicReset();
debug_print(PSTR("Init controller..."));
nic_write(NIC_PG0_IMR, 0);
nic_write(NIC_PG0_ISR, 0xff);
nic_write(NIC_CR, NIC_CR_STP | NIC_CR_RD2 | NIC_CR_PS0 | NIC_CR_PS1);
nic_write(NIC_PG3_EECR, NIC_EECR_EEM0 | NIC_EECR_EEM1);
nic_write(NIC_PG3_CONFIG3, 0);
nic_write(NIC_PG3_CONFIG2, NIC_CONFIG2_BSELB);
nic_write(NIC_PG3_EECR, 0);
/* Delay(50000);*/
delay_msec(2000);
nic_write(NIC_CR, NIC_CR_STP | NIC_CR_RD2);
nic_write(NIC_PG0_DCR, NIC_DCR_LS | NIC_DCR_FT1);
nic_write(NIC_PG0_RBCR0, 0);
nic_write(NIC_PG0_RBCR1, 0);
nic_write(NIC_PG0_RCR, NIC_RCR_MON);
nic_write(NIC_PG0_TCR, NIC_TCR_LB0);
nic_write(NIC_PG0_TPSR, NIC_FIRST_TX_PAGE);
nic_write(NIC_PG0_BNRY, NIC_STOP_PAGE - 1);
nic_write(NIC_PG0_PSTART, NIC_FIRST_RX_PAGE);
nic_write(NIC_PG0_PSTOP, NIC_STOP_PAGE);
nic_write(NIC_PG0_ISR, 0xff);
nic_write(NIC_CR, NIC_CR_STP | NIC_CR_RD2 | NIC_CR_PS0);
for(i = 0; i < 6; i++)
nic_write(NIC_PG1_PAR0 + i, mac[i]);
for(i = 0; i < 8; i++)
nic_write(NIC_PG1_MAR0 + i, 0);
nic_write(NIC_PG1_CURR, NIC_START_PAGE + TX_PAGES);
nic_write(NIC_CR, NIC_CR_STP | NIC_CR_RD2);
nic_write(NIC_PG0_RCR, NIC_RCR_AB);
nic_write(NIC_PG0_ISR, 0xff);
nic_write(NIC_PG0_IMR, 0);
nic_write(NIC_CR, NIC_CR_STA | NIC_CR_RD2);
nic_write(NIC_PG0_TCR, 0);
/* Delay(1000000)*/
delay_msec(2000);
nic_write(NIC_CR, NIC_CR_STA | NIC_CR_RD2 | NIC_CR_PS0 | NIC_CR_PS1);
rb = nic_read(NIC_PG3_CONFIG0);
debug_print8(rb);
switch(rb & 0xC0) {
case 0x00:
debug_print(PSTR("RTL8019AS "));
if(rb & 0x08)
debug_print(PSTR("jumper mode: "));
if(rb & 0x20)
debug_print(PSTR("AUI "));
if(rb & 0x10)
debug_print(PSTR("PNP "));
break;
case 0xC0:
debug_print(PSTR("RTL8019 "));
if(rb & 0x08)
debug_print(PSTR("jumper mode: "));
break;
default:
debug_print(PSTR("Unknown chip "));
debug_print8(rb);
break;
}
if(rb & 0x04)
debug_print(PSTR("BNC\x07 "));
if(rb & 0x03)
debug_print(PSTR("Failed\x07 "));
/* rb = nic_read(NIC_PG3_CONFIG1);
debug_print8(rb);*/
/* NutPrintFormat(0, "IRQ%u ", (rb >> 4) & 7);*/
/* debug_print("IRQ ");
debug_print8((rb >> 4) & 7);*/
rb = nic_read(NIC_PG3_CONFIG2);
debug_print8(rb);
switch(rb & 0xC0) {
case 0x00:
debug_print(PSTR("Auto "));
break;
case 0x40:
debug_print(PSTR("10BaseT "));
break;
case 0x80:
debug_print(PSTR("10Base5 "));
break;
case 0xC0:
debug_print(PSTR("10Base2 "));
break;
}
return;
/* HARD_RESET_RTL8019();*/
// do soft reset
writeRTL( ISR, readRTL(ISR) ) ;
delay_msec(50);
writeRTL(CR,0x21); // stop the NIC, abort DMA, page 0
delay_msec(2); // make sure nothing is coming in or going out
writeRTL(DCR, DCR_INIT); // 0x58
writeRTL(RBCR0,0x00);
writeRTL(RBCR1,0x00);
writeRTL(RCR,0x04);
writeRTL(TPSR, TXSTART_INIT);
writeRTL(TCR,0x02);
writeRTL(PSTART, RXSTART_INIT);
writeRTL(BNRY, RXSTART_INIT);
writeRTL(PSTOP, RXSTOP_INIT);
writeRTL(CR, 0x61);
delay_msec(2);
writeRTL(CURR, RXSTART_INIT);
writeRTL(PAR0+0, MYMAC_0);
writeRTL(PAR0+1, MYMAC_1);
writeRTL(PAR0+2, MYMAC_2);
writeRTL(PAR0+3, MYMAC_3);
writeRTL(PAR0+4, MYMAC_4);
writeRTL(PAR0+5, MYMAC_5);
writeRTL(CR,0x21);
writeRTL(DCR, DCR_INIT);
writeRTL(CR,0x22);
writeRTL(ISR,0xFF);
writeRTL(IMR, IMR_INIT);
writeRTL(TCR, TCR_INIT);
writeRTL(CR, 0x22); // start the NIC
}
/**
* Main TWI handler
*/
void twi_handler(void) {
struct ucinfo_t *info = &ucinfo;
if (ts_rx_valid == true) {
/* I must be a slave, I've received something */
switch (slave_rx_addr) {
case TWICMD_POWERUP:
/*
* Turn on a the power supply. If I'm getting this command, I'm a
* slave and I must have standby power on, so there must be a power
* supply on me. Separating this and TWICMD_STARTUP gets power to
* ALL slaves, even those without power supplies, for when the
* TWICMD_STARTUP happens.
*/
info->addressing_complete = false;
gpio_set_pin_high(SPARE_DOWN);
gpio_set_pin_high(HAVE_USB);
power_supply_on();
break;
case TWICMD_STARTUP:
/* restart addressing cycle */
info->addressing_complete = false;
gpio_set_pin_high(SPARE_DOWN);
gpio_set_pin_high(HAVE_USB);
usb_powerup_request();
break;
case TWICMD_POWERDOWN:
usb_powerdown_request();
break;
case TWICMD_ADDRESS:
if (tmp1 < sizeof(addresses) / sizeof(addresses[0])) {
addresses[tmp1] = slave_rx_data.b[0];
su_pin[tmp1] = gpio_pin_is_high(SPARE_UP);
sd_pin[tmp1] = gpio_pin_is_high(SPARE_DOWN);
tmp1++;
}
if (gpio_pin_is_low(SPARE_UP) && gpio_pin_is_high(SPARE_DOWN)) {
/* This is MY address! Grab it. */
my_twi_address = slave_rx_data.b[0];
my_twi_address_set = true;
delay_msec(1);
twi_slave_setup(my_twi_address);
delay_msec(1);
if (info->chain_configuration == CC_OPEN_UP) {
/*
* Send notification back up chain to master.
* Last address done
*/
gpio_set_pin_low(HAVE_USB);
} else {
/* Propagate down so next module gets next address. */
gpio_set_pin_low(SPARE_DOWN);
}
}
break;
case TWICMD_ADDRESSING_COMPLETE:
info->addressing_complete = true;
gpio_set_pin_high(SPARE_DOWN);
gpio_set_pin_high(HAVE_USB);
break;
case TWICMD_FPGA_ASIC_CTL:
fpga_reg_write(FA_ASIC_CONTROL,
(slave_rx_data.b[0] & F_FORCE_BAUD) ? (slave_rx_data.b[0] & ~F_FORCE_BAUD) : ((slave_rx_data.b[0] & ~F_ASIC_BAUD_MASK) | ucinfo.asic_baud_rate_code));
break;
case TWICMD_REBOOT:
if (slave_rx_nb && slave_rx_data.b[0]) {
/*
* Tell Atmel DFU loader not to start app ever again (harmless
* with custom loader).
*/
flashc_erase_gp_fuse_bit(31, true);
flashc_write_gp_fuse_bit(31, true);
/*
* Tell custom bootloader not to start app on this boot
* (harmless with Atmel DFU loader).
*/
AVR32_PM.gplp[1] = 0x73746179;
}
/* never returns */
self_reset();
break;
case TWICMD_FAN_SET:
set_fan_speed(slave_rx_data.b[0], slave_rx_data.b[1]);
break;
case TWICMD_DIE_SETTINGS:
if (slave_rx_nb) {
hf_nvram_write_die_settings(0, &slave_rx_data.opSettings);
}
break;
case TWICMD_BAD_CORE_BITMAP:
if (slave_rx_nb) {
hf_nvram_write_bad_core_bitmap(0, (((uint16_t) slave_rx_data.b[0]) << 8) | slave_rx_data.b[1]);
}
break;
case TWICMD_MIXED_BAUD:
set_mixed_slave_baudrate();
break;
case TWICMD_VOLTAGE_SET:
if (slave_rx_nb >= 3) {
module_voltage_set(0, slave_rx_data.b[0], ((uint16_t) slave_rx_data.b[1] << 8) | slave_rx_data.b[2]);
}
break;
default:
break;
}
ts_rx_valid = false;
}
if (info->master == false) {
if (info->addressing_complete == false) {
/* propagate HAVE_USB back up chain to master during address cycle */
if (info->chain_configuration == CC_MIDDLE) {
if (gpio_pin_is_high(USB_DOWN)) {
gpio_set_pin_high(HAVE_USB);
} else {
gpio_set_pin_low(HAVE_USB);
}
}
}
}
masterHandler();
}
void autonomous_routine1(void)
{
unsigned int sonar_distance = 0;
static unsigned long elapsed_time,
old_time = 0,
start_time;
controller_begin_autonomous_mode();
elapsed_time = start_time = SYSTEM_TIMER_SECONDS();
/*
* An autonomous loop with sensor input. Loop terminates when
* a button sensor on port 5 is pressed, or the 20 second time
* period runs out.
*/
forward1(MOTOR_POWER1);
while ( (elapsed_time - start_time) < ROUTINE1_DURATION )
{
sonar_distance = sonar_read(SONAR_INTERRUPT_PORT);
if ( (sonar_distance < ROUTINE1_SONAR_DISTANCE) ||
(io_read_digital(BUMPER_LEFT_PORT) == 0) ||
(io_read_digital(BUMPER_RIGHT_PORT) == 0) )
{
reverse1(MOTOR_POWER1);
delay_msec(ROUTINE1_BACKUP_MS);
sonar_distance = sonar_read(SONAR_INTERRUPT_PORT);
spin1(MOTOR_POWER1, ROUTINE1_SPIN_MS);
forward1(MOTOR_POWER1);
sonar_distance = sonar_read(SONAR_INTERRUPT_PORT);
}
elapsed_time = SYSTEM_TIMER_MS();
/* Adjust sonar direction every 40 ms */
if ( elapsed_time % ROUTINE1_SONAR_SERVO_DELAY == 0 )
sonar_scan(SONAR_SERVO_PORT);
/* Produce debug output once per second */
elapsed_time /= MS_PER_SEC;
if ( elapsed_time > old_time )
{
old_time = elapsed_time;
/*
if ( rc_new_data_available() )
{
DPRINTF("ET: %ld RC: %x A[1,2]: %x %x "
"D[5,6]: %d %d Shaft I[%d,%d]: %d %d Sonar[%d]: %d\n",
elapsed_time - start_time, rc_read_status(),
io_read_analog(1), io_read_analog(2),
io_read_digital(5), io_read_digital(6),
LEFT_ENCODER_INTERRUPT_PORT, RIGHT_ENCODER_INTERRUPT_PORT,
shaft_encoder_read_std(LEFT_ENCODER_INTERRUPT_PORT),
shaft_encoder_read_std(RIGHT_ENCODER_INTERRUPT_PORT),
SONAR_INTERRUPT_PORT, sonar_distance);
}
*/
}
}
pwm_write(RIGHT_DRIVE_PORT, MOTOR_STOP);
pwm_write(LEFT_DRIVE_PORT, MOTOR_STOP);
controller_submit_data(NO_WAIT);
controller_end_autonomous_mode();
}
