/*
** Return the compact node id of the node that ultimately "owns" the specified
** vertex. In order to do this, we walk back through masters and connect points
** until we reach a vertex that represents a node.
*/
cnodeid_t
master_node_get(devfs_handle_t vhdl)
{
cnodeid_t cnodeid;
devfs_handle_t master;
for (;;) {
cnodeid = nodevertex_to_cnodeid(vhdl);
if (cnodeid != CNODEID_NONE)
return(cnodeid);
master = device_master_get(vhdl);
/* Check for exceptional cases */
if (master == vhdl) {
/* Since we got a reference to the "master" thru
* device_master_get() we should decrement
* its reference count by 1
*/
return(CNODEID_NONE);
}
if (master == GRAPH_VERTEX_NONE) {
master = hwgraph_connectpt_get(vhdl);
if ((master == GRAPH_VERTEX_NONE) ||
(master == vhdl)) {
return(CNODEID_NONE);
}
}
vhdl = master;
}
}
/*
* hub_device_inquiry
* Find out the xtalk widget related information stored in this
* hub's II.
*/
void
hub_device_inquiry(devfs_handle_t xbus_vhdl, xwidgetnum_t widget)
{
devfs_handle_t xconn, hub_vhdl;
char widget_name[8];
hubreg_t ii_iidem,ii_iiwa, ii_iowa;
hubinfo_t hubinfo;
nasid_t nasid;
int d;
sprintf(widget_name, "%d", widget);
if (hwgraph_traverse(xbus_vhdl, widget_name, &xconn)
!= GRAPH_SUCCESS)
return;
hub_vhdl = device_master_get(xconn);
if (hub_vhdl == GRAPH_VERTEX_NONE)
return;
hubinfo_get(hub_vhdl, &hubinfo);
if (!hubinfo)
return;
nasid = hubinfo->h_nasid;
ii_iidem = REMOTE_HUB_L(nasid, IIO_IIDEM);
ii_iiwa = REMOTE_HUB_L(nasid, IIO_IIWA);
ii_iowa = REMOTE_HUB_L(nasid, IIO_IOWA);
#if defined(SUPPORT_PRINTING_V_FORMAT)
cmn_err(CE_CONT, "Inquiry Info for %v\n", xconn);
#else
cmn_err(CE_CONT, "Inquiry Info for 0x%p\n", &xconn);
#endif
cmn_err(CE_CONT,"\tDevices shutdown [ ");
for (d = 0 ; d <= 7 ; d++)
if (!(ii_iidem & (IIO_IIDEM_WIDGETDEV_MASK(widget,d))))
cmn_err(CE_CONT, " %d", d);
cmn_err(CE_CONT,"]\n");
cmn_err(CE_CONT,
"\tInbound access ? %s\n",
ii_iiwa & IIO_IIWA_WIDGET(widget) ? "yes" : "no");
cmn_err(CE_CONT,
"\tOutbound access ? %s\n",
ii_iowa & IIO_IOWA_WIDGET(widget) ? "yes" : "no");
}
/* Define the system critical vertices and connect them through
* a canonical parent-child relationships for easy traversal
* during io error handling.
*/
static void
sys_critical_graph_init(void)
{
devfs_handle_t bridge_vhdl,master_node_vhdl;
devfs_handle_t xbow_vhdl = GRAPH_VERTEX_NONE;
extern devfs_handle_t hwgraph_root;
devfs_handle_t pci_slot_conn;
int slot;
devfs_handle_t baseio_console_conn;
DBG("sys_critical_graph_init: FIXME.\n");
baseio_console_conn = hwgraph_connectpt_get(baseio_console_vhdl);
if (baseio_console_conn == NULL) {
return;
}
/* Get the vertex handle for the baseio bridge */
bridge_vhdl = device_master_get(baseio_console_conn);
/* Get the master node of the baseio card */
master_node_vhdl = cnodeid_to_vertex(
master_node_get(baseio_console_vhdl));
/* Add the "root->node" part of the system critical graph */
sys_critical_graph_vertex_add(hwgraph_root,master_node_vhdl);
/* Check if we have a crossbow */
if (hwgraph_traverse(master_node_vhdl,
EDGE_LBL_XTALK"/0",
&xbow_vhdl) == GRAPH_SUCCESS) {
/* We have a crossbow.Add "node->xbow" part of the system
* critical graph.
*/
sys_critical_graph_vertex_add(master_node_vhdl,xbow_vhdl);
/* Add "xbow->baseio bridge" of the system critical graph */
sys_critical_graph_vertex_add(xbow_vhdl,bridge_vhdl);
hwgraph_vertex_unref(xbow_vhdl);
} else
/* We donot have a crossbow. Add "node->baseio_bridge"
* part of the system critical graph.
*/
sys_critical_graph_vertex_add(master_node_vhdl,bridge_vhdl);
/* Add all the populated PCI slot vertices to the system critical
* graph with the bridge vertex as the parent.
*/
for (slot = 0 ; slot < 8; slot++) {
char slot_edge[10];
sprintf(slot_edge,"%d",slot);
if (hwgraph_traverse(bridge_vhdl,slot_edge, &pci_slot_conn)
!= GRAPH_SUCCESS)
continue;
sys_critical_graph_vertex_add(bridge_vhdl,pci_slot_conn);
hwgraph_vertex_unref(pci_slot_conn);
}
hwgraph_vertex_unref(bridge_vhdl);
/* Add the "ioc3 pci connection point -> console ioc3" part
* of the system critical graph
*/
if (hwgraph_traverse(baseio_console_vhdl,"..",&pci_slot_conn) ==
GRAPH_SUCCESS) {
sys_critical_graph_vertex_add(pci_slot_conn,
baseio_console_vhdl);
hwgraph_vertex_unref(pci_slot_conn);
}
/* Add the "ethernet pci connection point -> base ethernet" part of
* the system critical graph
*/
if (hwgraph_traverse(baseio_enet_vhdl,"..",&pci_slot_conn) ==
GRAPH_SUCCESS) {
sys_critical_graph_vertex_add(pci_slot_conn,
baseio_enet_vhdl);
hwgraph_vertex_unref(pci_slot_conn);
}
/* Add the "scsi controller pci connection point -> base scsi
* controller" part of the system critical graph
*/
if (hwgraph_traverse(base_io_scsi_ctlr_vhdl[0],
"../..",&pci_slot_conn) == GRAPH_SUCCESS) {
sys_critical_graph_vertex_add(pci_slot_conn,
base_io_scsi_ctlr_vhdl[0]);
hwgraph_vertex_unref(pci_slot_conn);
}
if (hwgraph_traverse(base_io_scsi_ctlr_vhdl[1],
"../..",&pci_slot_conn) == GRAPH_SUCCESS) {
sys_critical_graph_vertex_add(pci_slot_conn,
base_io_scsi_ctlr_vhdl[1]);
hwgraph_vertex_unref(pci_slot_conn);
}
hwgraph_vertex_unref(baseio_console_conn);
}
/*
* pci_bus_map_create() - Called by pci_bus_to_hcl_cvlink() to finish the job.
*
* Linux PCI Bus numbers are assigned from lowest module_id numbers
* (rack/slot etc.) starting from HUB_WIDGET_ID_MAX down to
* HUB_WIDGET_ID_MIN:
* widgetnum 15 gets lower Bus Number than widgetnum 14 etc.
*
* Given 2 modules 001c01 and 001c02 we get the following mappings:
* 001c01, widgetnum 15 = Bus number 0
* 001c01, widgetnum 14 = Bus number 1
* 001c02, widgetnum 15 = Bus number 3
* 001c02, widgetnum 14 = Bus number 4
* etc.
*
* The rational for starting Bus Number 0 with Widget number 15 is because
* the system boot disks are always connected via Widget 15 Slot 0 of the
* I-brick. Linux creates /dev/sd* devices(naming) strating from Bus Number 0
* Therefore, /dev/sda1 will be the first disk, on Widget 15 of the lowest
* module id(Master Cnode) of the system.
*
*/
static int
pci_bus_map_create(devfs_handle_t xtalk)
{
devfs_handle_t master_node_vertex = NULL;
devfs_handle_t xwidget = NULL;
devfs_handle_t pci_bus = NULL;
hubinfo_t hubinfo = NULL;
xwidgetnum_t widgetnum;
char pathname[128];
graph_error_t rv;
/*
* Loop throught this vertex and get the Xwidgets ..
*/
for (widgetnum = HUB_WIDGET_ID_MAX; widgetnum >= HUB_WIDGET_ID_MIN; widgetnum--) {
#if 0
{
int pos;
char dname[256];
pos = devfs_generate_path(xtalk, dname, 256);
printk("%s : path= %s\n", __FUNCTION__, &dname[pos]);
}
#endif
sprintf(pathname, "%d", widgetnum);
xwidget = NULL;
/*
* Example - /hw/module/001c16/Pbrick/xtalk/8 is the xwidget
* /hw/module/001c16/Pbrick/xtalk/8/pci/1 is device
*/
rv = hwgraph_traverse(xtalk, pathname, &xwidget);
if ( (rv != GRAPH_SUCCESS) ) {
if (!xwidget)
continue;
}
sprintf(pathname, "%d/"EDGE_LBL_PCI, widgetnum);
pci_bus = NULL;
if (hwgraph_traverse(xtalk, pathname, &pci_bus) != GRAPH_SUCCESS)
if (!pci_bus)
continue;
/*
* Assign the correct bus number and also the nasid of this
* pci Xwidget.
*
* Should not be any race here ...
*/
num_bridges++;
busnum_to_pcibr_vhdl[num_bridges - 1] = pci_bus;
/*
* Get the master node and from there get the NASID.
*/
master_node_vertex = device_master_get(xwidget);
if (!master_node_vertex) {
printk("WARNING: pci_bus_map_create: Unable to get .master for vertex 0x%p\n", (void *)xwidget);
}
hubinfo_get(master_node_vertex, &hubinfo);
if (!hubinfo) {
printk("WARNING: pci_bus_map_create: Unable to get hubinfo for master node vertex 0x%p\n", (void *)master_node_vertex);
return(1);
} else {
busnum_to_nid[num_bridges - 1] = hubinfo->h_nasid;
}
/*
* Pre assign DMA maps needed for 32 Bits Page Map DMA.
*/
busnum_to_atedmamaps[num_bridges - 1] = (void *) kmalloc(
sizeof(struct sn_dma_maps_s) * MAX_ATE_MAPS, GFP_KERNEL);
if (!busnum_to_atedmamaps[num_bridges - 1])
printk("WARNING: pci_bus_map_create: Unable to precreate ATE DMA Maps for busnum %d vertex 0x%p\n", num_bridges - 1, (void *)xwidget);
memset(busnum_to_atedmamaps[num_bridges - 1], 0x0,
sizeof(struct sn_dma_maps_s) * MAX_ATE_MAPS);
}
return(0);
}
