static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) { int i; int num; char *property = "g-tx-fifo-size"; struct dwc2_core_params *p = &hsotg->params; memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); /* Read tx fifo sizes */ num = device_property_read_u32_array(hsotg->dev, property, NULL, 0); if (num > 0) { device_property_read_u32_array(hsotg->dev, property, &p->g_tx_fifo_size[1], num); } else { u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE; memcpy(&p->g_tx_fifo_size[1], p_tx_fifo, sizeof(p_tx_fifo)); num = ARRAY_SIZE(p_tx_fifo); } for (i = 0; i < num; i++) { if ((i + 1) >= ARRAY_SIZE(p->g_tx_fifo_size)) break; dev_dbg(hsotg->dev, "Setting %s[%d] to %d\n", property, i + 1, p->g_tx_fifo_size[i + 1]); } }
/** * dwc2_get_device_properties() - Read in device properties. * * Read in the device properties and adjust core parameters if needed. */ static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg) { struct dwc2_core_params *p = &hsotg->params; int num; if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || (hsotg->dr_mode == USB_DR_MODE_OTG)) { device_property_read_u32(hsotg->dev, "g-rx-fifo-size", &p->g_rx_fifo_size); device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size", &p->g_np_tx_fifo_size); num = device_property_read_u32_array(hsotg->dev, "g-tx-fifo-size", NULL, 0); if (num > 0) { num = min(num, 15); memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); device_property_read_u32_array(hsotg->dev, "g-tx-fifo-size", &p->g_tx_fifo_size[1], num); } } }
static int stm32_dmamux_probe(struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; const struct of_device_id *match; struct device_node *dma_node; struct stm32_dmamux_data *stm32_dmamux; struct resource *res; void __iomem *iomem; int i, count, ret; u32 dma_req; if (!node) return -ENODEV; count = device_property_read_u32_array(&pdev->dev, "dma-masters", NULL, 0); if (count < 0) { dev_err(&pdev->dev, "Can't get DMA master(s) node\n"); return -ENODEV; } stm32_dmamux = devm_kzalloc(&pdev->dev, sizeof(*stm32_dmamux) + sizeof(u32) * (count + 1), GFP_KERNEL); if (!stm32_dmamux) return -ENOMEM; dma_req = 0; for (i = 1; i <= count; i++) { dma_node = of_parse_phandle(node, "dma-masters", i - 1); match = of_match_node(stm32_stm32dma_master_match, dma_node); if (!match) { dev_err(&pdev->dev, "DMA master is not supported\n"); of_node_put(dma_node); return -EINVAL; } if (of_property_read_u32(dma_node, "dma-requests", &stm32_dmamux->dma_reqs[i])) { dev_info(&pdev->dev, "Missing MUX output information, using %u.\n", STM32_DMAMUX_MAX_DMA_REQUESTS); stm32_dmamux->dma_reqs[i] = STM32_DMAMUX_MAX_DMA_REQUESTS; } dma_req += stm32_dmamux->dma_reqs[i]; of_node_put(dma_node); } if (dma_req > STM32_DMAMUX_MAX_DMA_REQUESTS) { dev_err(&pdev->dev, "Too many DMA Master Requests to manage\n"); return -ENODEV; } stm32_dmamux->dma_requests = dma_req; stm32_dmamux->dma_reqs[0] = count; stm32_dmamux->dma_inuse = devm_kcalloc(&pdev->dev, BITS_TO_LONGS(dma_req), sizeof(unsigned long), GFP_KERNEL); if (!stm32_dmamux->dma_inuse) return -ENOMEM; if (device_property_read_u32(&pdev->dev, "dma-requests", &stm32_dmamux->dmamux_requests)) { stm32_dmamux->dmamux_requests = STM32_DMAMUX_MAX_REQUESTS; dev_warn(&pdev->dev, "DMAMUX defaulting on %u requests\n", stm32_dmamux->dmamux_requests); } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) return -ENODEV; iomem = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(iomem)) return PTR_ERR(iomem); spin_lock_init(&stm32_dmamux->lock); stm32_dmamux->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(stm32_dmamux->clk)) { ret = PTR_ERR(stm32_dmamux->clk); if (ret == -EPROBE_DEFER) dev_info(&pdev->dev, "Missing controller clock\n"); return ret; } stm32_dmamux->rst = devm_reset_control_get(&pdev->dev, NULL); if (!IS_ERR(stm32_dmamux->rst)) { reset_control_assert(stm32_dmamux->rst); udelay(2); reset_control_deassert(stm32_dmamux->rst); } stm32_dmamux->iomem = iomem; stm32_dmamux->dmarouter.dev = &pdev->dev; stm32_dmamux->dmarouter.route_free = stm32_dmamux_free; platform_set_drvdata(pdev, stm32_dmamux); if (!IS_ERR(stm32_dmamux->clk)) { ret = clk_prepare_enable(stm32_dmamux->clk); if (ret < 0) { dev_err(&pdev->dev, "clk_prep_enable error: %d\n", ret); return ret; } } /* Reset the dmamux */ for (i = 0; i < stm32_dmamux->dma_requests; i++) stm32_dmamux_write(stm32_dmamux->iomem, STM32_DMAMUX_CCR(i), 0); if (!IS_ERR(stm32_dmamux->clk)) clk_disable(stm32_dmamux->clk); return of_dma_router_register(node, stm32_dmamux_route_allocate, &stm32_dmamux->dmarouter); }
/* set global incr burst type configuration registers */ static void dwc3_set_incr_burst_type(struct dwc3 *dwc) { struct device *dev = dwc->dev; /* incrx_mode : for INCR burst type. */ bool incrx_mode; /* incrx_size : for size of INCRX burst. */ u32 incrx_size; u32 *vals; u32 cfg; int ntype; int ret; int i; cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); /* * Handle property "snps,incr-burst-type-adjustment". * Get the number of value from this property: * result <= 0, means this property is not supported. * result = 1, means INCRx burst mode supported. * result > 1, means undefined length burst mode supported. */ ntype = device_property_read_u32_array(dev, "snps,incr-burst-type-adjustment", NULL, 0); if (ntype <= 0) return; vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); if (!vals) { dev_err(dev, "Error to get memory\n"); return; } /* Get INCR burst type, and parse it */ ret = device_property_read_u32_array(dev, "snps,incr-burst-type-adjustment", vals, ntype); if (ret) { dev_err(dev, "Error to get property\n"); return; } incrx_size = *vals; if (ntype > 1) { /* INCRX (undefined length) burst mode */ incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; for (i = 1; i < ntype; i++) { if (vals[i] > incrx_size) incrx_size = vals[i]; } } else { /* INCRX burst mode */ incrx_mode = INCRX_BURST_MODE; } /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; if (incrx_mode) cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; switch (incrx_size) { case 256: cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; break; case 128: cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; break; case 64: cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; break; case 32: cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; break; case 16: cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; break; case 8: cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; break; case 4: cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; break; case 1: break; default: dev_err(dev, "Invalid property\n"); break; } dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); }
static int xgbe_probe(struct platform_device *pdev) { struct xgbe_prv_data *pdata; struct net_device *netdev; struct device *dev = &pdev->dev, *phy_dev; struct platform_device *phy_pdev; struct resource *res; const char *phy_mode; unsigned int i, phy_memnum, phy_irqnum; enum dev_dma_attr attr; int ret; DBGPR("--> xgbe_probe\n"); netdev = alloc_etherdev_mq(sizeof(struct xgbe_prv_data), XGBE_MAX_DMA_CHANNELS); if (!netdev) { dev_err(dev, "alloc_etherdev failed\n"); ret = -ENOMEM; goto err_alloc; } SET_NETDEV_DEV(netdev, dev); pdata = netdev_priv(netdev); pdata->netdev = netdev; pdata->pdev = pdev; pdata->adev = ACPI_COMPANION(dev); pdata->dev = dev; platform_set_drvdata(pdev, netdev); spin_lock_init(&pdata->lock); spin_lock_init(&pdata->xpcs_lock); mutex_init(&pdata->rss_mutex); spin_lock_init(&pdata->tstamp_lock); pdata->msg_enable = netif_msg_init(debug, default_msg_level); set_bit(XGBE_DOWN, &pdata->dev_state); /* Check if we should use ACPI or DT */ pdata->use_acpi = dev->of_node ? 0 : 1; phy_pdev = xgbe_get_phy_pdev(pdata); if (!phy_pdev) { dev_err(dev, "unable to obtain phy device\n"); ret = -EINVAL; goto err_phydev; } phy_dev = &phy_pdev->dev; if (pdev == phy_pdev) { /* New style device tree or ACPI: * The XGBE and PHY resources are grouped together with * the PHY resources listed last */ phy_memnum = xgbe_resource_count(pdev, IORESOURCE_MEM) - 3; phy_irqnum = xgbe_resource_count(pdev, IORESOURCE_IRQ) - 1; } else { /* Old style device tree: * The XGBE and PHY resources are separate */ phy_memnum = 0; phy_irqnum = 0; } /* Set and validate the number of descriptors for a ring */ BUILD_BUG_ON_NOT_POWER_OF_2(XGBE_TX_DESC_CNT); pdata->tx_desc_count = XGBE_TX_DESC_CNT; if (pdata->tx_desc_count & (pdata->tx_desc_count - 1)) { dev_err(dev, "tx descriptor count (%d) is not valid\n", pdata->tx_desc_count); ret = -EINVAL; goto err_io; } BUILD_BUG_ON_NOT_POWER_OF_2(XGBE_RX_DESC_CNT); pdata->rx_desc_count = XGBE_RX_DESC_CNT; if (pdata->rx_desc_count & (pdata->rx_desc_count - 1)) { dev_err(dev, "rx descriptor count (%d) is not valid\n", pdata->rx_desc_count); ret = -EINVAL; goto err_io; } /* Obtain the mmio areas for the device */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); pdata->xgmac_regs = devm_ioremap_resource(dev, res); if (IS_ERR(pdata->xgmac_regs)) { dev_err(dev, "xgmac ioremap failed\n"); ret = PTR_ERR(pdata->xgmac_regs); goto err_io; } if (netif_msg_probe(pdata)) dev_dbg(dev, "xgmac_regs = %p\n", pdata->xgmac_regs); res = platform_get_resource(pdev, IORESOURCE_MEM, 1); pdata->xpcs_regs = devm_ioremap_resource(dev, res); if (IS_ERR(pdata->xpcs_regs)) { dev_err(dev, "xpcs ioremap failed\n"); ret = PTR_ERR(pdata->xpcs_regs); goto err_io; } if (netif_msg_probe(pdata)) dev_dbg(dev, "xpcs_regs = %p\n", pdata->xpcs_regs); res = platform_get_resource(phy_pdev, IORESOURCE_MEM, phy_memnum++); pdata->rxtx_regs = devm_ioremap_resource(dev, res); if (IS_ERR(pdata->rxtx_regs)) { dev_err(dev, "rxtx ioremap failed\n"); ret = PTR_ERR(pdata->rxtx_regs); goto err_io; } if (netif_msg_probe(pdata)) dev_dbg(dev, "rxtx_regs = %p\n", pdata->rxtx_regs); res = platform_get_resource(phy_pdev, IORESOURCE_MEM, phy_memnum++); pdata->sir0_regs = devm_ioremap_resource(dev, res); if (IS_ERR(pdata->sir0_regs)) { dev_err(dev, "sir0 ioremap failed\n"); ret = PTR_ERR(pdata->sir0_regs); goto err_io; } if (netif_msg_probe(pdata)) dev_dbg(dev, "sir0_regs = %p\n", pdata->sir0_regs); res = platform_get_resource(phy_pdev, IORESOURCE_MEM, phy_memnum++); pdata->sir1_regs = devm_ioremap_resource(dev, res); if (IS_ERR(pdata->sir1_regs)) { dev_err(dev, "sir1 ioremap failed\n"); ret = PTR_ERR(pdata->sir1_regs); goto err_io; } if (netif_msg_probe(pdata)) dev_dbg(dev, "sir1_regs = %p\n", pdata->sir1_regs); /* Retrieve the MAC address */ ret = device_property_read_u8_array(dev, XGBE_MAC_ADDR_PROPERTY, pdata->mac_addr, sizeof(pdata->mac_addr)); if (ret || !is_valid_ether_addr(pdata->mac_addr)) { dev_err(dev, "invalid %s property\n", XGBE_MAC_ADDR_PROPERTY); if (!ret) ret = -EINVAL; goto err_io; } /* Retrieve the PHY mode - it must be "xgmii" */ ret = device_property_read_string(dev, XGBE_PHY_MODE_PROPERTY, &phy_mode); if (ret || strcmp(phy_mode, phy_modes(PHY_INTERFACE_MODE_XGMII))) { dev_err(dev, "invalid %s property\n", XGBE_PHY_MODE_PROPERTY); if (!ret) ret = -EINVAL; goto err_io; } pdata->phy_mode = PHY_INTERFACE_MODE_XGMII; /* Check for per channel interrupt support */ if (device_property_present(dev, XGBE_DMA_IRQS_PROPERTY)) pdata->per_channel_irq = 1; /* Retrieve the PHY speedset */ ret = device_property_read_u32(phy_dev, XGBE_SPEEDSET_PROPERTY, &pdata->speed_set); if (ret) { dev_err(dev, "invalid %s property\n", XGBE_SPEEDSET_PROPERTY); goto err_io; } switch (pdata->speed_set) { case XGBE_SPEEDSET_1000_10000: case XGBE_SPEEDSET_2500_10000: break; default: dev_err(dev, "invalid %s property\n", XGBE_SPEEDSET_PROPERTY); ret = -EINVAL; goto err_io; } /* Retrieve the PHY configuration properties */ if (device_property_present(phy_dev, XGBE_BLWC_PROPERTY)) { ret = device_property_read_u32_array(phy_dev, XGBE_BLWC_PROPERTY, pdata->serdes_blwc, XGBE_SPEEDS); if (ret) { dev_err(dev, "invalid %s property\n", XGBE_BLWC_PROPERTY); goto err_io; } } else { memcpy(pdata->serdes_blwc, xgbe_serdes_blwc, sizeof(pdata->serdes_blwc)); } if (device_property_present(phy_dev, XGBE_CDR_RATE_PROPERTY)) { ret = device_property_read_u32_array(phy_dev, XGBE_CDR_RATE_PROPERTY, pdata->serdes_cdr_rate, XGBE_SPEEDS); if (ret) { dev_err(dev, "invalid %s property\n", XGBE_CDR_RATE_PROPERTY); goto err_io; } } else { memcpy(pdata->serdes_cdr_rate, xgbe_serdes_cdr_rate, sizeof(pdata->serdes_cdr_rate)); } if (device_property_present(phy_dev, XGBE_PQ_SKEW_PROPERTY)) { ret = device_property_read_u32_array(phy_dev, XGBE_PQ_SKEW_PROPERTY, pdata->serdes_pq_skew, XGBE_SPEEDS); if (ret) { dev_err(dev, "invalid %s property\n", XGBE_PQ_SKEW_PROPERTY); goto err_io; } } else { memcpy(pdata->serdes_pq_skew, xgbe_serdes_pq_skew, sizeof(pdata->serdes_pq_skew)); } if (device_property_present(phy_dev, XGBE_TX_AMP_PROPERTY)) { ret = device_property_read_u32_array(phy_dev, XGBE_TX_AMP_PROPERTY, pdata->serdes_tx_amp, XGBE_SPEEDS); if (ret) { dev_err(dev, "invalid %s property\n", XGBE_TX_AMP_PROPERTY); goto err_io; } } else { memcpy(pdata->serdes_tx_amp, xgbe_serdes_tx_amp, sizeof(pdata->serdes_tx_amp)); } if (device_property_present(phy_dev, XGBE_DFE_CFG_PROPERTY)) { ret = device_property_read_u32_array(phy_dev, XGBE_DFE_CFG_PROPERTY, pdata->serdes_dfe_tap_cfg, XGBE_SPEEDS); if (ret) { dev_err(dev, "invalid %s property\n", XGBE_DFE_CFG_PROPERTY); goto err_io; } } else { memcpy(pdata->serdes_dfe_tap_cfg, xgbe_serdes_dfe_tap_cfg, sizeof(pdata->serdes_dfe_tap_cfg)); } if (device_property_present(phy_dev, XGBE_DFE_ENA_PROPERTY)) { ret = device_property_read_u32_array(phy_dev, XGBE_DFE_ENA_PROPERTY, pdata->serdes_dfe_tap_ena, XGBE_SPEEDS); if (ret) { dev_err(dev, "invalid %s property\n", XGBE_DFE_ENA_PROPERTY); goto err_io; } } else { memcpy(pdata->serdes_dfe_tap_ena, xgbe_serdes_dfe_tap_ena, sizeof(pdata->serdes_dfe_tap_ena)); } /* Obtain device settings unique to ACPI/OF */ if (pdata->use_acpi) ret = xgbe_acpi_support(pdata); else ret = xgbe_of_support(pdata); if (ret) goto err_io; /* Set the DMA coherency values */ attr = device_get_dma_attr(dev); if (attr == DEV_DMA_NOT_SUPPORTED) { dev_err(dev, "DMA is not supported"); goto err_io; } pdata->coherent = (attr == DEV_DMA_COHERENT); if (pdata->coherent) { pdata->axdomain = XGBE_DMA_OS_AXDOMAIN; pdata->arcache = XGBE_DMA_OS_ARCACHE; pdata->awcache = XGBE_DMA_OS_AWCACHE; } else { pdata->axdomain = XGBE_DMA_SYS_AXDOMAIN; pdata->arcache = XGBE_DMA_SYS_ARCACHE; pdata->awcache = XGBE_DMA_SYS_AWCACHE; } /* Get the device interrupt */ ret = platform_get_irq(pdev, 0); if (ret < 0) { dev_err(dev, "platform_get_irq 0 failed\n"); goto err_io; } pdata->dev_irq = ret; /* Get the auto-negotiation interrupt */ ret = platform_get_irq(phy_pdev, phy_irqnum++); if (ret < 0) { dev_err(dev, "platform_get_irq phy 0 failed\n"); goto err_io; } pdata->an_irq = ret; netdev->irq = pdata->dev_irq; netdev->base_addr = (unsigned long)pdata->xgmac_regs; memcpy(netdev->dev_addr, pdata->mac_addr, netdev->addr_len); /* Set all the function pointers */ xgbe_init_all_fptrs(pdata); /* Issue software reset to device */ pdata->hw_if.exit(pdata); /* Populate the hardware features */ xgbe_get_all_hw_features(pdata); /* Set default configuration data */ xgbe_default_config(pdata); /* Set the DMA mask */ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(pdata->hw_feat.dma_width)); if (ret) { dev_err(dev, "dma_set_mask_and_coherent failed\n"); goto err_io; } /* Calculate the number of Tx and Rx rings to be created * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set * the number of Tx queues to the number of Tx channels * enabled * -Rx (DMA) Channels do not map 1-to-1 so use the actual * number of Rx queues */ pdata->tx_ring_count = min_t(unsigned int, num_online_cpus(), pdata->hw_feat.tx_ch_cnt); pdata->tx_q_count = pdata->tx_ring_count; ret = netif_set_real_num_tx_queues(netdev, pdata->tx_ring_count); if (ret) { dev_err(dev, "error setting real tx queue count\n"); goto err_io; } pdata->rx_ring_count = min_t(unsigned int, netif_get_num_default_rss_queues(), pdata->hw_feat.rx_ch_cnt); pdata->rx_q_count = pdata->hw_feat.rx_q_cnt; ret = netif_set_real_num_rx_queues(netdev, pdata->rx_ring_count); if (ret) { dev_err(dev, "error setting real rx queue count\n"); goto err_io; } /* Initialize RSS hash key and lookup table */ netdev_rss_key_fill(pdata->rss_key, sizeof(pdata->rss_key)); for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++) XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, i % pdata->rx_ring_count); XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1); XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1); XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1); /* Call MDIO/PHY initialization routine */ pdata->phy_if.phy_init(pdata); /* Set device operations */ netdev->netdev_ops = xgbe_get_netdev_ops(); netdev->ethtool_ops = xgbe_get_ethtool_ops(); #ifdef CONFIG_AMD_XGBE_DCB netdev->dcbnl_ops = xgbe_get_dcbnl_ops(); #endif /* Set device features */ netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GRO | NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_FILTER; if (pdata->hw_feat.rss) netdev->hw_features |= NETIF_F_RXHASH; netdev->vlan_features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_TSO | NETIF_F_TSO6; netdev->features |= netdev->hw_features; pdata->netdev_features = netdev->features; netdev->priv_flags |= IFF_UNICAST_FLT; /* Use default watchdog timeout */ netdev->watchdog_timeo = 0; xgbe_init_rx_coalesce(pdata); xgbe_init_tx_coalesce(pdata); netif_carrier_off(netdev); ret = register_netdev(netdev); if (ret) { dev_err(dev, "net device registration failed\n"); goto err_io; } /* Create the PHY/ANEG name based on netdev name */ snprintf(pdata->an_name, sizeof(pdata->an_name) - 1, "%s-pcs", netdev_name(netdev)); /* Create workqueues */ pdata->dev_workqueue = create_singlethread_workqueue(netdev_name(netdev)); if (!pdata->dev_workqueue) { netdev_err(netdev, "device workqueue creation failed\n"); ret = -ENOMEM; goto err_netdev; } pdata->an_workqueue = create_singlethread_workqueue(pdata->an_name); if (!pdata->an_workqueue) { netdev_err(netdev, "phy workqueue creation failed\n"); ret = -ENOMEM; goto err_wq; } xgbe_ptp_register(pdata); xgbe_debugfs_init(pdata); platform_device_put(phy_pdev); netdev_notice(netdev, "net device enabled\n"); DBGPR("<-- xgbe_probe\n"); return 0; err_wq: destroy_workqueue(pdata->dev_workqueue); err_netdev: unregister_netdev(netdev); err_io: platform_device_put(phy_pdev); err_phydev: free_netdev(netdev); err_alloc: dev_notice(dev, "net device not enabled\n"); return ret; }
static int amd_xgbe_phy_probe(struct phy_device *phydev) { struct amd_xgbe_phy_priv *priv; struct platform_device *phy_pdev; struct device *dev, *phy_dev; unsigned int phy_resnum, phy_irqnum; int ret; if (!phydev->bus || !phydev->bus->parent) return -EINVAL; dev = phydev->bus->parent; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; priv->pdev = to_platform_device(dev); priv->adev = ACPI_COMPANION(dev); priv->dev = dev; priv->phydev = phydev; mutex_init(&priv->an_mutex); INIT_WORK(&priv->an_irq_work, amd_xgbe_an_irq_work); INIT_WORK(&priv->an_work, amd_xgbe_an_state_machine); if (!priv->adev || acpi_disabled) { struct device_node *bus_node; struct device_node *phy_node; bus_node = priv->dev->of_node; phy_node = of_parse_phandle(bus_node, "phy-handle", 0); if (!phy_node) { dev_err(dev, "unable to parse phy-handle\n"); ret = -EINVAL; goto err_priv; } phy_pdev = of_find_device_by_node(phy_node); of_node_put(phy_node); if (!phy_pdev) { dev_err(dev, "unable to obtain phy device\n"); ret = -EINVAL; goto err_priv; } phy_resnum = 0; phy_irqnum = 0; } else { /* In ACPI, the XGBE and PHY resources are the grouped * together with the PHY resources at the end */ phy_pdev = priv->pdev; phy_resnum = amd_xgbe_phy_resource_count(phy_pdev, IORESOURCE_MEM) - 3; phy_irqnum = amd_xgbe_phy_resource_count(phy_pdev, IORESOURCE_IRQ) - 1; } phy_dev = &phy_pdev->dev; /* Get the device mmio areas */ priv->rxtx_res = platform_get_resource(phy_pdev, IORESOURCE_MEM, phy_resnum++); priv->rxtx_regs = devm_ioremap_resource(dev, priv->rxtx_res); if (IS_ERR(priv->rxtx_regs)) { dev_err(dev, "rxtx ioremap failed\n"); ret = PTR_ERR(priv->rxtx_regs); goto err_put; } priv->sir0_res = platform_get_resource(phy_pdev, IORESOURCE_MEM, phy_resnum++); priv->sir0_regs = devm_ioremap_resource(dev, priv->sir0_res); if (IS_ERR(priv->sir0_regs)) { dev_err(dev, "sir0 ioremap failed\n"); ret = PTR_ERR(priv->sir0_regs); goto err_rxtx; } priv->sir1_res = platform_get_resource(phy_pdev, IORESOURCE_MEM, phy_resnum++); priv->sir1_regs = devm_ioremap_resource(dev, priv->sir1_res); if (IS_ERR(priv->sir1_regs)) { dev_err(dev, "sir1 ioremap failed\n"); ret = PTR_ERR(priv->sir1_regs); goto err_sir0; } /* Get the auto-negotiation interrupt */ ret = platform_get_irq(phy_pdev, phy_irqnum); if (ret < 0) { dev_err(dev, "platform_get_irq failed\n"); goto err_sir1; } priv->an_irq = ret; /* Get the device speed set property */ ret = device_property_read_u32(phy_dev, XGBE_PHY_SPEEDSET_PROPERTY, &priv->speed_set); if (ret) { dev_err(dev, "invalid %s property\n", XGBE_PHY_SPEEDSET_PROPERTY); goto err_sir1; } switch (priv->speed_set) { case AMD_XGBE_PHY_SPEEDSET_1000_10000: case AMD_XGBE_PHY_SPEEDSET_2500_10000: break; default: dev_err(dev, "invalid %s property\n", XGBE_PHY_SPEEDSET_PROPERTY); ret = -EINVAL; goto err_sir1; } if (device_property_present(phy_dev, XGBE_PHY_BLWC_PROPERTY)) { ret = device_property_read_u32_array(phy_dev, XGBE_PHY_BLWC_PROPERTY, priv->serdes_blwc, XGBE_PHY_SPEEDS); if (ret) { dev_err(dev, "invalid %s property\n", XGBE_PHY_BLWC_PROPERTY); goto err_sir1; } } else { memcpy(priv->serdes_blwc, amd_xgbe_phy_serdes_blwc, sizeof(priv->serdes_blwc)); } if (device_property_present(phy_dev, XGBE_PHY_CDR_RATE_PROPERTY)) { ret = device_property_read_u32_array(phy_dev, XGBE_PHY_CDR_RATE_PROPERTY, priv->serdes_cdr_rate, XGBE_PHY_SPEEDS); if (ret) { dev_err(dev, "invalid %s property\n", XGBE_PHY_CDR_RATE_PROPERTY); goto err_sir1; } } else { memcpy(priv->serdes_cdr_rate, amd_xgbe_phy_serdes_cdr_rate, sizeof(priv->serdes_cdr_rate)); } if (device_property_present(phy_dev, XGBE_PHY_PQ_SKEW_PROPERTY)) { ret = device_property_read_u32_array(phy_dev, XGBE_PHY_PQ_SKEW_PROPERTY, priv->serdes_pq_skew, XGBE_PHY_SPEEDS); if (ret) { dev_err(dev, "invalid %s property\n", XGBE_PHY_PQ_SKEW_PROPERTY); goto err_sir1; } } else { memcpy(priv->serdes_pq_skew, amd_xgbe_phy_serdes_pq_skew, sizeof(priv->serdes_pq_skew)); } if (device_property_present(phy_dev, XGBE_PHY_TX_AMP_PROPERTY)) { ret = device_property_read_u32_array(phy_dev, XGBE_PHY_TX_AMP_PROPERTY, priv->serdes_tx_amp, XGBE_PHY_SPEEDS); if (ret) { dev_err(dev, "invalid %s property\n", XGBE_PHY_TX_AMP_PROPERTY); goto err_sir1; } } else { memcpy(priv->serdes_tx_amp, amd_xgbe_phy_serdes_tx_amp, sizeof(priv->serdes_tx_amp)); } phydev->priv = priv; if (!priv->adev || acpi_disabled) platform_device_put(phy_pdev); return 0; err_sir1: devm_iounmap(dev, priv->sir1_regs); devm_release_mem_region(dev, priv->sir1_res->start, resource_size(priv->sir1_res)); err_sir0: devm_iounmap(dev, priv->sir0_regs); devm_release_mem_region(dev, priv->sir0_res->start, resource_size(priv->sir0_res)); err_rxtx: devm_iounmap(dev, priv->rxtx_regs); devm_release_mem_region(dev, priv->rxtx_res->start, resource_size(priv->rxtx_res)); err_put: if (!priv->adev || acpi_disabled) platform_device_put(phy_pdev); err_priv: devm_kfree(dev, priv); return ret; }