static void cache_ramstage(void)
{
/* Enable caching for lower 1MB and ram stage using variable mtrr */
disable_cache();
set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
enable_cache();
}
static void command_data(struct udc_ep *ep, struct udc_req *req)
{
struct udc *udc = ep->dev;
struct udc_ep *ep1 = &udc->ep[1];
switch (cmd) {
case COMMAND_LOAD:
if (req->actual != sizeof(struct load_data))
return;
struct load_data *load = req->buf;
bzero(&buffer_req, sizeof(buffer_req));
INIT_LIST_HEAD(&buffer_req.queue);
buffer_req.buf = load->addr;
buffer_req.length = load->length;
ep1->ops->queue(ep1, &buffer_req);
break;
case COMMAND_RUN:
if (req->actual != sizeof(struct run_data))
return;
struct run_data *run = req->buf;
disable_cache();
run->f();
break;
}
}
void cache_as_ram_new_stack (void)
{
void *resume_backup_memory = NULL;
print_car_debug("Top about %08x ... Done\n", (uint32_t) &resume_backup_memory);
print_car_debug("Disabling cache as ram now\n");
disable_cache_as_ram_bsp();
disable_cache();
/* Enable cached access to RAM in the range 1M to CONFIG_RAMTOP */
set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
enable_cache();
if (acpi_is_wakeup_s3()) {
resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
print_car_debug("Resume backup memory location: %p\n", resume_backup_memory);
}
prepare_ramstage_region(resume_backup_memory);
set_sysinfo_in_ram(1); // So other core0 could start to train mem
/*copy and execute ramstage */
copy_and_run();
/* We will not return */
print_car_debug("should not be here -\n");
}
static void set_init_ecc_mtrrs(void)
{
msr_t msr;
int i;
disable_cache();
/* First clear all of the msrs to be safe */
for (i = 0; i < MTRR_COUNT; i++) {
msr_t zero;
zero.lo = zero.hi = 0;
wrmsr(MTRR_PHYS_BASE(i), zero);
wrmsr(MTRR_PHYS_MASK(i), zero);
}
/* Write back cache the first 1MB */
msr.hi = 0x00000000;
msr.lo = 0x00000000 | MTRR_TYPE_WRBACK;
wrmsr(MTRR_PHYS_BASE(0), msr);
msr.hi = 0x000000ff;
msr.lo = ~((CONFIG_RAMTOP) - 1) | 0x800;
wrmsr(MTRR_PHYS_MASK(0), msr);
/* Set the default type to write combining */
msr.hi = 0x00000000;
msr.lo = 0xc00 | MTRR_TYPE_WRCOMB;
wrmsr(MTRR_DEF_TYPE_MSR, msr);
/* Set TOP_MEM to 4G */
msr.hi = 0x00000001;
msr.lo = 0x00000000;
wrmsr(TOP_MEM, msr);
enable_cache();
}
/*********************************************************************
* init_main - Main entry point for initialisation code *
**********************************************************************/
void init_main(void)
{
init_clock_config();
/* Disable interrupts, watchdog timer, cache */
disable_interrupts();
disable_watchdog_timer();
disable_cache();
/* Initialise individual modules */
init_cache();
init_crossbar();
init_chip_selects();
init_eport();
init_flexcan();
init_dma_timers();
init_interrupt_timers();
init_real_time_clock();
init_watchdog_timers();
init_edma();
init_pin_assignments();
/* Initialise SDRAM controller (must be done after pin assignments) */
init_sdram_controller();
/* Initialise interrupt controller */
init_interrupt_controller();
}
void cmd_execute(ether_header_t * ether, ip_header_t * ip, udp_header_t * udp, command_t * command)
{
if (!running) {
tool_ip = ntohl(ip->src);
tool_port = ntohs(udp->src);
memcpy(tool_mac, ether->src, 6);
our_ip = ntohl(ip->dest);
make_ip(ntohl(ip->src), ntohl(ip->dest), UDP_H_LEN + COMMAND_LEN, 17, (ip_header_t *)(pkt_buf + ETHER_H_LEN));
make_udp(ntohs(udp->src), ntohs(udp->dest),(unsigned char *) command, COMMAND_LEN, (ip_header_t *)(pkt_buf + ETHER_H_LEN), (udp_header_t *)(pkt_buf + ETHER_H_LEN + IP_H_LEN));
eth_txts(pkt_buf, ETHER_H_LEN + IP_H_LEN + UDP_H_LEN + COMMAND_LEN);
#if 0
printf("executing %p ...", ntohl(command->address));
if (ntohl(command->size)&1)
*(unsigned int *)0x8c004004 = 0xdeadbeef; /* enable console */
else
*(unsigned int *)0x8c004004 = 0xfeedface; /* disable console */
irq_disable();
disable_cache();
go(ntohl(command->address));
#endif
}
}
static void model_10_init(device_t dev)
{
printk(BIOS_DEBUG, "Model 10 Init - a no-op.\n");
u8 i;
msr_t msr;
#if CONFIG_LOGICAL_CPUS
u32 siblings;
#endif
/* Turn on caching if we haven't already */
x86_enable_cache();
amd_setup_mtrrs();
x86_mtrr_check();
disable_cache();
/* zero the machine check error status registers */
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < 6; i++) {
wrmsr(MCI_STATUS + (i * 4), msr);
}
enable_cache();
/* Enable the local cpu apics */
setup_lapic();
/* Set the processor name string */
// init_processor_name();
#if CONFIG_LOGICAL_CPUS
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
msr.lo |= 1 << 28;
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
msr.hi |= 1 << (33 - 32);
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
#endif
/* DisableCf8ExtCfg */
msr = rdmsr(NB_CFG_MSR);
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
/* Write protect SMM space with SMMLOCK. */
msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0);
wrmsr(HWCR_MSR, msr);
}
void setup_cache()
{
#ifdef USE_CACHE
enable_cache();
#else
disable_cache();
#endif
}
void smm_init(void)
{
msr_t msr, syscfg_orig, mtrr_aseg_orig;
/* Back up MSRs for later restore */
syscfg_orig = rdmsr(SYSCFG_MSR);
mtrr_aseg_orig = rdmsr(MTRRfix16K_A0000_MSR);
/* MTRR changes don't like an enabled cache */
disable_cache();
msr = syscfg_orig;
/* Allow changes to MTRR extended attributes */
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
/* turn the extended attributes off until we fix
* them so A0000 is routed to memory
*/
msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
/* set DRAM access to 0xa0000 */
msr.lo = 0x18181818;
msr.hi = 0x18181818;
wrmsr(MTRRfix16K_A0000_MSR, msr);
/* enable the extended features */
msr = syscfg_orig;
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
enable_cache();
/* copy the real SMM handler */
memcpy((void *)SMM_BASE, &_binary_smm_start, (size_t)&_binary_smm_size);
wbinvd();
disable_cache();
/* Restore SYSCFG and MTRR */
wrmsr(SYSCFG_MSR, syscfg_orig);
wrmsr(MTRRfix16K_A0000_MSR, mtrr_aseg_orig);
enable_cache();
/* CPU MSR are set in CPU init */
}
static void enable_rom_caching(void)
{
msr_t msr;
disable_cache();
/* Why only top 4MiB ? */
set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT);
enable_cache();
/* Enable Variable MTRRs */
msr.hi = 0x00000000;
msr.lo = 0x00000800;
wrmsr(MTRRdefType_MSR, msr);
}
static void enable_rom_caching(void)
{
msr_t msr;
disable_cache();
set_var_mtrr(1, 0xffffffff - CACHE_ROM_SIZE + 1,
CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
enable_cache();
/* Enable Variable MTRRs */
msr.hi = 0x00000000;
msr.lo = 0x00000800;
wrmsr(MTRR_DEF_TYPE_MSR, msr);
}
static void restore_mtrr_state(struct mtrr_state *state)
{
int i;
disable_cache();
for (i = 0; i < MTRR_COUNT; i++) {
wrmsr(MTRRphysBase_MSR(i), state->mtrrs[i].base);
wrmsr(MTRRphysMask_MSR(i), state->mtrrs[i].mask);
}
wrmsr(TOP_MEM, state->top_mem);
wrmsr(TOP_MEM2, state->top_mem2);
wrmsr(MTRRdefType_MSR, state->def_type);
enable_cache();
}
static void restore_mtrr_state(struct mtrr_state *state)
{
int i;
disable_cache();
for (i = 0; i < MTRR_COUNT; i++) {
wrmsr(MTRR_PHYS_BASE(i), state->mtrrs[i].base);
wrmsr(MTRR_PHYS_MASK(i), state->mtrrs[i].mask);
}
wrmsr(TOP_MEM, state->top_mem);
wrmsr(TOP_MEM2, state->top_mem2);
wrmsr(MTRR_DEF_TYPE_MSR, state->def_type);
enable_cache();
}
static inline void early_mtrr_init(void)
{
static const unsigned long mtrr_msrs[] = {
/* fixed mtrr */
0x250, 0x258, 0x259,
0x268, 0x269, 0x26A,
0x26B, 0x26C, 0x26D,
0x26E, 0x26F,
/* var mtrr */
0x200, 0x201, 0x202, 0x203,
0x204, 0x205, 0x206, 0x207,
0x208, 0x209, 0x20A, 0x20B,
0x20C, 0x20D, 0x20E, 0x20F,
/* NULL end of table */
0
};
disable_cache();
do_early_mtrr_init(mtrr_msrs);
enable_cache();
}
asmlinkage void cache_as_ram_new_stack(void)
{
print_car_debug("Disabling cache as RAM now\n");
disable_cache_as_ram_real(0); // inline
disable_cache();
/* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */
set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
enable_cache();
prepare_ramstage_region(acpi_is_wakeup_s3());
set_sysinfo_in_ram(1); // So other core0 could start to train mem
/*copy and execute ramstage */
copy_and_run();
/* We will not return */
print_car_debug("should not be here -\n");
}
int run_discs_config(GList **config)
{
int ret = fwife_question(_("Do you want to search for a installation CD/DVD?\n\n"
"If you want an installation from a CD/DVD, you should answer 'Yes'.\n"
"Otherwise if you want a network installation, you should answer 'No'"));
/* if the user whant a cd/dvd install */
if(ret == GTK_RESPONSE_YES) {
if(run_discs_detection(config)) {
char *pacbindir = g_strdup_printf("%s/frugalware-%s", SOURCEDIR, ARCH);
disable_cache(pacbindir);
FREE(pacbindir);
skip_to_next_plugin();
return 1;
} else {
fwife_error("No package database found.\nPerforming a network installation.");
}
}
return 0;
}
void ACPI::shadow_bios(void)
{
printf("Shadowing BIOS");
void *area = malloc(SHADOW_LEN);
xassert(area);
memcpy(area, (void *)SHADOW_BASE, SHADOW_LEN);
// disable fixed MTRRs
uint64_t val = lib::rdmsr(MSR_SYSCFG);
lib::wrmsr(MSR_SYSCFG, val | (3 << 18));
disable_cache();
lib::wrmsr(MSR_MTRR_FIX4K_F0000, FMTRR_WRITETHROUGH);
lib::wrmsr(MSR_MTRR_FIX4K_F8000, FMTRR_WRITETHROUGH);
enable_cache();
// reenable fixed MTRRs
lib::wrmsr(MSR_SYSCFG, val | (1 << 18));
memcpy((void *)SHADOW_BASE, area, SHADOW_LEN);
free(area);
printf("\n");
bios_shadowed = 1;
}
void restore_mtrr(void)
{
volatile UINT32 *msrPtr = (volatile UINT32 *)S3_DATA_MTRR_POS;
msr_t msr_data;
u32 i;
printk(BIOS_SPEW, "%s\n", __func__);
disable_cache();
/* Enable access to AMD RdDram and WrDram extension bits */
msr_data = rdmsr(SYS_CFG);
msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn;
wrmsr(SYS_CFG, msr_data);
/* Restore the Fixed MTRRs */
for (i = 0; i < (u32)sizeof(mtrr_table_fixed_MTRR)/sizeof(u32); i++) {
msr_data.lo = *msrPtr;
msrPtr ++;
msr_data.hi = *msrPtr;
msrPtr ++;
wrmsr(mtrr_table_fixed_MTRR[i], msr_data);
}
/* Disable access to AMD RdDram and WrDram extension bits */
msr_data = rdmsr(SYS_CFG);
msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
wrmsr(SYS_CFG, msr_data);
/* Restore the Variable MTRRs, SYS_CFG, TOM, TOM2 */
for (i = 0; i < (u32)sizeof(mtrr_table_var_MTRR)/sizeof(u32); i++) {
msr_data.lo = *msrPtr;
msrPtr ++;
msr_data.hi = *msrPtr;
msrPtr ++;
wrmsr(mtrr_table_var_MTRR[i], msr_data);
}
}
int dc_main(void)
{
unsigned long bin_size = 0xfeedbeef;
char tmp_str[8];
vid_init(vid_check_cable(), DM_640x480, PM_RGB565);
vid_clear(0,100,0);
/* Relocate the 1st_read.bin */
bin_size = *((unsigned long *) REAL_LOAD_POINT);
uint_to_string(bin_size, tmp_str);
bfont_draw_str(vram_s+10*640+20, 640, "bin_size = ");
bfont_draw_str(vram_s+50*640+20, 640, tmp_str);
memmove((unsigned char *) REAL_LOAD_POINT, (unsigned char *) LOADED_POINT, bin_size);
dbr_set(ubc_works);
vbr_set(vbr_buffer);
*UBC_R_BARA = (unsigned int) BREAKPOINT;
*UBC_R_BAMRA = (1<<2);
*UBC_R_BBRA = (1<<5) | (1<<4) | (1<<3) | (1<<2);
*UBC_R_BRCR = (1<<10) | (1<<15) | 1;
ubc_wait();
ubc_wait();
ubc_wait();
ubc_wait();
vid_clear(50,0,50);
disable_cache();
(*(void (*)()) REAL_LOAD_POINT) ();
vid_init(vid_check_cable(), DM_640x480, PM_RGB565);
vid_clear(100,0,0);
bfont_draw_str(vram_s+100*640+20, 640, "[UBC] DANGER! We're returned from the game!");
while(1);
}
void smm_init(void)
{
msr_t msr;
msr = rdmsr(HWCR_MSR);
if (msr.lo & (1 << 0)) {
// This sounds like a bug... ?
printk(BIOS_DEBUG, "SMM is still locked from last boot, using old handler.\n");
return;
}
/* Only copy SMM handler once, not once per CPU */
if (!smm_handler_copied) {
msr_t syscfg_orig, mtrr_aseg_orig;
smm_handler_copied = 1;
/* Back up MSRs for later restore */
syscfg_orig = rdmsr(SYSCFG_MSR);
mtrr_aseg_orig = rdmsr(MTRRfix16K_A0000_MSR);
/* MTRR changes don't like an enabled cache */
disable_cache();
msr = syscfg_orig;
/* Allow changes to MTRR extended attributes */
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
/* turn the extended attributes off until we fix
* them so A0000 is routed to memory
*/
msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
/* set DRAM access to 0xa0000 */
/* A0000 is memory */
msr.lo = 0x18181818;
msr.hi = 0x18181818;
wrmsr(MTRRfix16K_A0000_MSR, msr);
/* enable the extended features */
msr = syscfg_orig;
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
enable_cache();
/* copy the real SMM handler */
memcpy((void *)SMM_BASE, &_binary_smm_start, (size_t)&_binary_smm_size);
wbinvd();
/* Restore MTRR */
disable_cache();
/* Restore SYSCFG */
wrmsr(SYSCFG_MSR, syscfg_orig);
wrmsr(MTRRfix16K_A0000_MSR, mtrr_aseg_orig);
enable_cache();
}
/* But set SMM base address on all CPUs/cores */
msr = rdmsr(SMM_BASE_MSR);
msr.lo = SMM_BASE - (lapicid() * 0x400);
wrmsr(SMM_BASE_MSR, msr);
/* enable the SMM memory window */
msr = rdmsr(SMM_MASK_MSR);
msr.lo |= (1 << 0); // Enable ASEG SMRAM Range
wrmsr(SMM_MASK_MSR, msr);
/* Set SMMLOCK to avoid exploits messing with SMM */
msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0);
wrmsr(HWCR_MSR, msr);
}
int run(GList **config)
{
GList *partlist;
char **nrdevs, *ptr, *op, *np, *dest;
int ret;
char my_buffer[MAX_LEN + 1] = "";
detect_parts(0);
// select swap partitions to use
partlist = selswap();
// format swap partitions
if(doswap(partlist, config) == -1)
return(-1);
// root partition
ptr = selrootdev();
if(ptr == NULL)
return(-1);
if(formatdev(ptr) == -1)
return(-1);
mountdev(ptr, "/", config);
// move temporarily stuff to the final location
chdir(TARGETDIR);
np = g_strdup_printf("%s/%s", TARGETDIR, "/etc/profile.d");
makepath(np);
FREE(np);
op = (char*)data_get(*config, "fstab");
np = g_strdup_printf("%s/%s", TARGETDIR, "/etc/fstab");
copyfile(op, np);
unlink(op);
chmod (np, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
data_put(config, "fstab", strdup(np));
FREE(np);
np = g_strdup_printf("%s/%s", TARGETDIR, "/etc/sysconfig");
makepath(np);
FREE(np);
// so that 1) the user can't mount a partition as /dev because
// it'll be used 2) install scriptlets will be able to do
// >/dev/null
makepath(TARGETDIR "/dev");
makepath(TARGETDIR "/proc");
makepath(TARGETDIR "/sys");
fw_system("mount none -t devtmpfs " TARGETDIR "/dev");
fw_system("mount none -t proc " TARGETDIR "/proc");
fw_system("mount none -t sysfs " TARGETDIR "/sys");
// non-root partitions
dialog_vars.backtitle=gen_backtitle(_("Selecting other partitions"));
while(1)
{
dialog_vars.input_result = my_buffer;
nrdevs = parts2dialog(parts);
dlg_put_backtitle();
dlg_clear();
dialog_vars.cancel_label = _("Continue");
dialog_vars.input_result = my_buffer;
dialog_vars.input_result[0]='\0';
ret = dialog_menu(
_("Select other Linux partitions for /etc/fstab"),
_("You may use your other partitions to distribute your Linux "
"system across more than one partition. Currently, you have "
"only mounted your / partition. You might want to mount "
"directories such as /boot, /home or /usr/local on separate "
"partitions. You should not try to mount /usr, /etc, /sbin or "
"/bin on their own partitions since they contain utilities "
"needed to bring the system up and mount partitions. Also, "
"do not reuse a partition that you've already entered before. "
"Please select one of the partitions listed below, or if "
"you're done, hit Continue."),
0, 0, 0, g_list_length(parts)/2, nrdevs);
dialog_vars.cancel_label = '\0';
FREE(nrdevs);
if (ret != DLG_EXIT_CANCEL)
{
if(!strcmp(_("(in use)"), dialog_vars.input_result))
continue;
ptr = strdup(dialog_vars.input_result);
if(formatdev(ptr) == -1)
return(-1);
dest = asktowhere(ptr);
if(dest == NULL)
return(-1);
mountdev(ptr, dest, config);
FREE(dest);
FREE(ptr);
}
else
break;
}
makepath(g_strdup_printf("%s/%s", TARGETDIR, "/var/log"));
np = g_strdup_printf("%s/%s", TARGETDIR, LOGFILE);
copyfile(LOGFILE, np);
unlink(LOGFILE);
chmod (np, S_IRUSR|S_IWUSR);
FREE(np);
// disable caching for cds
// this is needed here since when the cds is loaded we had no
// formatted root partition
if((char*)data_get(*config, "netinstall")==NULL)
{
char *pacbindir = g_strdup_printf("%s/frugalware-%s", SOURCEDIR, ARCH);
char *ptr;
ptr = g_strdup_printf("%s/var/cache/pacman-g2/pkg", TARGETDIR);
makepath(ptr);
FREE(ptr);
disable_cache(pacbindir);
FREE(pacbindir);
}
return(0);
}
static void model_15_init(device_t dev)
{
printk(BIOS_DEBUG, "Model 15 Init.\n");
u8 i;
msr_t msr;
int msrno;
unsigned int cpu_idx;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
u32 siblings;
#endif
//x86_enable_cache();
//amd_setup_mtrrs();
//x86_mtrr_check();
disable_cache ();
/* Enable access to AMD RdDram and WrDram extension bits */
msr = rdmsr(SYSCFG_MSR);
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
// BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
msr.lo = msr.hi = 0;
wrmsr (0x259, msr);
msr.lo = msr.hi = 0x1e1e1e1e;
wrmsr(0x250, msr);
wrmsr(0x258, msr);
for (msrno = 0x268; msrno <= 0x26f; msrno++)
wrmsr (msrno, msr);
msr = rdmsr(SYSCFG_MSR);
msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
if (acpi_is_wakeup())
restore_mtrr();
x86_mtrr_check();
x86_enable_cache();
/* zero the machine check error status registers */
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < 6; i++) {
wrmsr(MCI_STATUS + (i * 4), msr);
}
/* Enable the local cpu apics */
setup_lapic();
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
msr.lo |= 1 << 28;
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
msr.hi |= 1 << (33 - 32);
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
#endif
/* DisableCf8ExtCfg */
msr = rdmsr(NB_CFG_MSR);
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
cpu_idx = cpu_info()->index;
printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);
/* Set SMM base address for this CPU */
msr = rdmsr(MSR_SMM_BASE);
msr.lo = SMM_BASE - (cpu_idx * 0x400);
wrmsr(MSR_SMM_BASE, msr);
/* Enable the SMM memory window */
msr = rdmsr(MSR_SMM_MASK);
msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */
wrmsr(MSR_SMM_MASK, msr);
}
/* Write protect SMM space with SMMLOCK. */
msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0);
wrmsr(HWCR_MSR, msr);
}
static void model_15_init(device_t dev)
{
printk(BIOS_DEBUG, "Model 15 Init.\n");
u8 i;
msr_t msr;
int msrno;
#if CONFIG_LOGICAL_CPUS
u32 siblings;
#endif
disable_cache();
/* Enable access to AMD RdDram and WrDram extension bits */
msr = rdmsr(SYSCFG_MSR);
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
// BSP: make a0000-bffff UC, c0000-fffff WB
msr.lo = msr.hi = 0;
wrmsr(0x259, msr);
msr.lo = msr.hi = 0x1e1e1e1e;
wrmsr(0x250, msr);
wrmsr(0x258, msr);
for (msrno = 0x268; msrno <= 0x26f; msrno++)
wrmsr(msrno, msr);
msr = rdmsr(SYSCFG_MSR);
msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
if (acpi_is_wakeup())
restore_mtrr();
x86_mtrr_check();
x86_enable_cache();
/* zero the machine check error status registers */
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < 6; i++)
wrmsr(MCI_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */
setup_lapic();
#if CONFIG_LOGICAL_CPUS
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
msr.lo |= 1 << 28;
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
msr.hi |= 1 << (33 - 32);
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
#endif
PSPProgBar3Msr(NULL);
/* DisableCf8ExtCfg */
msr = rdmsr(NB_CFG_MSR);
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
/* Write protect SMM space with SMMLOCK. */
msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0);
wrmsr(HWCR_MSR, msr);
}
static void model_10xxx_init(device_t dev)
{
u8 i;
msr_t msr;
struct node_core_id id;
#if CONFIG_LOGICAL_CPUS
u32 siblings;
#endif
id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */
printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
/* Turn on caching if we haven't already */
x86_enable_cache();
amd_setup_mtrrs();
x86_mtrr_check();
disable_cache();
/* zero the machine check error status registers */
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < 5; i++) {
wrmsr(MCI_STATUS + (i * 4), msr);
}
enable_cache();
/* Enable the local cpu apics */
setup_lapic();
/* Set the processor name string */
init_processor_name();
#if CONFIG_LOGICAL_CPUS
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
msr.lo |= 1 << 28;
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
msr.hi |= 1 << (33 - 32);
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
#endif
/* DisableCf8ExtCfg */
msr = rdmsr(NB_CFG_MSR);
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
msr = rdmsr(BU_CFG2_MSR);
/* Clear ClLinesToNbDis */
msr.lo &= ~(1 << 15);
/* Clear bit 35 as per Erratum 343 */
msr.hi &= ~(1 << (35-32));
wrmsr(BU_CFG2_MSR, msr);
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
printk(BIOS_DEBUG, "Initializing SMM ASeg memory\n");
/* Set SMM base address for this CPU */
msr = rdmsr(SMM_BASE_MSR);
msr.lo = SMM_BASE - (lapicid() * 0x400);
wrmsr(SMM_BASE_MSR, msr);
/* Enable the SMM memory window */
msr = rdmsr(SMM_MASK_MSR);
msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */
wrmsr(SMM_MASK_MSR, msr);
} else {
printk(BIOS_DEBUG, "Disabling SMM ASeg memory\n");
/* Set SMM base address for this CPU */
msr = rdmsr(SMM_BASE_MSR);
msr.lo = SMM_BASE - (lapicid() * 0x400);
wrmsr(SMM_BASE_MSR, msr);
/* Disable the SMM memory window */
msr.hi = 0x0;
msr.lo = 0x0;
wrmsr(SMM_MASK_MSR, msr);
}
/* Set SMMLOCK to avoid exploits messing with SMM */
msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0);
wrmsr(HWCR_MSR, msr);
}
void restore_mtrr(void)
{
volatile u32 *msrPtr = (u32 *) OemS3Saved_MTRR_Storage();
u32 msr;
msr_t msr_data;
if (!msrPtr)
return;
disable_cache();
/* Enable access to AMD RdDram and WrDram extension bits */
msr_data = rdmsr(SYSCFG_MSR);
msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn;
wrmsr(SYSCFG_MSR, msr_data);
/* Now restore the Fixed MTRRs */
msr_data.lo = *msrPtr;
msrPtr ++;
msr_data.hi = *msrPtr;
msrPtr ++;
wrmsr(0x250, msr_data);
msr_data.lo = *msrPtr;
msrPtr ++;
msr_data.hi = *msrPtr;
msrPtr ++;
wrmsr(0x258, msr_data);
msr_data.lo = *msrPtr;
msrPtr ++;
msr_data.hi = *msrPtr;
msrPtr ++;
wrmsr(0x259, msr_data);
for (msr = 0x268; msr <= 0x26F; msr++) {
msr_data.lo = *msrPtr;
msrPtr ++;
msr_data.hi = *msrPtr;
msrPtr ++;
wrmsr(msr, msr_data);
}
/* Disable access to AMD RdDram and WrDram extension bits */
msr_data = rdmsr(SYSCFG_MSR);
msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
wrmsr(SYSCFG_MSR, msr_data);
/* Restore the Variable MTRRs */
for (msr = 0x200; msr <= 0x20F; msr++) {
msr_data.lo = *msrPtr;
msrPtr ++;
msr_data.hi = *msrPtr;
msrPtr ++;
wrmsr(msr, msr_data);
}
/* Restore SYSCFG MTRR */
msr_data.lo = *msrPtr;
msrPtr ++;
msr_data.hi = *msrPtr;
msrPtr ++;
wrmsr(SYSCFG_MSR, msr_data);
}
int run(GList **config)
{
GList *drives=NULL;
int i;
int found = 0;
char *ptr;
umount_if_needed(SOURCEDIR);
dialog_vars.backtitle=gen_backtitle(_("Selecting source media"));
dlg_put_backtitle();
dlg_clear();
dialog_msgbox(_("Scanning"), _("Scanning for a CD/DVD drive containing "
"a Frugalware install disc..."), 0, 0, 0);
drives = grep_drives("/proc/sys/dev/cdrom/info");
for (i=0; i<g_list_length(drives); i++)
{
ptr = get_blkid((char*)g_list_nth_data(drives, i));
if(ptr && !strcmp(ptr, "Frugalware Install"))
{
LOG("install medium found in %s", (char*)g_list_nth_data(drives, i));
FREE(ptr);
ptr = g_strdup_printf("mount -o ro -t iso9660 /dev/%s %s", (char*)g_list_nth_data(drives, i),
SOURCEDIR);
fw_system(ptr);
data_put(config, "srcdev", (char*)g_list_nth_data(drives, i));
dlg_put_backtitle();
dialog_msgbox(_("CD/DVD drive found"), g_strdup_printf(_("A Frugalware install disc was found in device /dev/%s."), (char*)g_list_nth_data(drives, i)), 0, 0, 0);
if(is_netinstall(SOURCEDIR))
{
data_put(config, "netinstall", "");
LOG("install medium contains no packages, performing a network installation");
}
else
LOG("install medium contains packages, performing an offline installation");
found = 1;
break;
}
else
LOG("skipping non-install medium in %s", (char*)g_list_nth_data(drives, i));
FREE(ptr);
}
if(!found)
{
LOG("no package database found, performing a network installation");
data_put(config, "netinstall", "");
}
// disable caching for cds
if((char*)data_get(*config, "netinstall")==NULL)
{
char *pacbindir = g_strdup_printf("%s/frugalware-%s", SOURCEDIR, ARCH);
disable_cache(pacbindir);
FREE(pacbindir);
}
if(data_get(*config, "srcdev")==NULL)
{
LOG("no cd/dvd drive found, this is normal if you are running setup from a pendrive or in an emulator");
}
return(0);
}
static void model_14_init(device_t dev)
{
u32 i;
msr_t msr;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
u32 siblings;
#endif
printk(BIOS_DEBUG, "Model 14 Init.\n");
disable_cache ();
/*
* AGESA sets the MTRRs main MTRRs. The shadow area needs to be set
* by coreboot. The amd_setup_mtrrs should work, but needs debug on fam14.
* TODO:
* amd_setup_mtrrs();
*/
/* Enable access to AMD RdDram and WrDram extension bits */
msr = rdmsr(SYSCFG_MSR);
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
/* Set shadow WB, RdMEM, WrMEM */
msr.lo = msr.hi = 0;
wrmsr (0x259, msr);
msr.hi = msr.lo = 0x1e1e1e1e;
wrmsr(0x250, msr);
wrmsr(0x258, msr);
for (i = 0x268; i <= 0x26f; i++)
wrmsr(i, msr);
msr = rdmsr(SYSCFG_MSR);
msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
if (acpi_is_wakeup())
restore_mtrr();
x86_mtrr_check();
x86_enable_cache();
/* zero the machine check error status registers */
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < 6; i++) {
wrmsr(MCI_STATUS + (i * 4), msr);
}
/* Enable the local cpu apics */
setup_lapic();
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
msr.lo |= 1 << 28;
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
msr.hi |= 1 << (33 - 32);
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
#endif
/* DisableCf8ExtCfg */
msr = rdmsr(NB_CFG_MSR);
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
/* Write protect SMM space with SMMLOCK. */
msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0);
wrmsr(HWCR_MSR, msr);
printk(BIOS_SPEW, "%s done.\n", __func__);
}
static void model_16_init(struct device *dev)
{
printk(BIOS_DEBUG, "Model 16 Init.\n");
u8 i;
msr_t msr;
int num_banks;
int msrno;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
u32 siblings;
#endif
//x86_enable_cache();
//amd_setup_mtrrs();
//x86_mtrr_check();
disable_cache();
/* Enable access to AMD RdDram and WrDram extension bits */
msr = rdmsr(SYSCFG_MSR);
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
// BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
msr.lo = msr.hi = 0;
wrmsr(MTRR_FIX_16K_A0000, msr);
msr.lo = msr.hi = 0x1e1e1e1e;
wrmsr(MTRR_FIX_64K_00000, msr);
wrmsr(MTRR_FIX_16K_80000, msr);
for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++)
wrmsr(msrno, msr);
msr = rdmsr(SYSCFG_MSR);
msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
if (acpi_is_wakeup())
restore_mtrr();
x86_mtrr_check();
x86_enable_cache();
/* zero the machine check error status registers */
msr = rdmsr(IA32_MCG_CAP);
num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < num_banks; i++)
wrmsr(IA32_MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */
setup_lapic();
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
msr.lo |= 1 << 28;
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
msr.hi |= 1 << (33 - 32);
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
#endif
/* DisableCf8ExtCfg */
msr = rdmsr(NB_CFG_MSR);
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
/* Write protect SMM space with SMMLOCK. */
msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0);
wrmsr(HWCR_MSR, msr);
}
static void model_12_init(device_t dev)
{
printk(BIOS_DEBUG, "Model 12 Init.\n");
u8 i;
msr_t msr;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
u32 siblings;
#endif
// struct node_core_id id;
// id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */
// printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
/* Turn on caching if we haven't already */
x86_enable_cache();
amd_setup_mtrrs();
x86_mtrr_check();
disable_cache();
/* zero the machine check error status registers */
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < 5; i++) {
wrmsr(MCI_STATUS + (i * 4), msr);
}
enable_cache();
/* Enable the local CPU apics */
setup_lapic();
/* Set the processor name string */
// init_processor_name();
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
msr.lo |= 1 << 28;
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
msr.hi |= 1 << (33 - 32);
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
#endif
/* DisableCf8ExtCfg */
msr = rdmsr(NB_CFG_MSR);
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
/* Write protect SMM space with SMMLOCK. */
msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0);
wrmsr(HWCR_MSR, msr);
}