int meson_power_suspend(void)
{
static int test_flag = 0;
unsigned addr;
unsigned p_addr;
void (*pwrtest_entry)(unsigned,unsigned,unsigned,unsigned);
check_in_param();
flush_cache_all();
addr = 0x04F04400;//entry.s start
p_addr = (unsigned)__phys_to_virt(addr);
pwrtest_entry = (void (*)(unsigned,unsigned,unsigned,unsigned))p_addr;
if(test_flag != 1234){
test_flag = 1234;
printk("initial appf\n");
pwrtest_entry(APPF_INITIALIZE,0,0,IO_PL310_BASE & 0xffff0000);
}
if(AML_WDT_ENABLED){
disable_watchdog();
if(awdtv)
enable_watchdog(awdtv->firmware_timeout*awdtv->one_second);
}
printk("power down cpu --\n");
pwrtest_entry(APPF_POWER_DOWN_CPU,0,0,APPF_SAVE_PMU|APPF_SAVE_VFP|APPF_SAVE_L2 |( IO_PL310_BASE & 0xffff0000));
if(AML_WDT_ENABLED){
disable_watchdog();
if(awdtv)
enable_watchdog(awdtv->suspend_timeout*awdtv->one_second);
}
return 0;
}
int meson_power_suspend(void)
{
static int test_flag = 0;
unsigned addr;
unsigned p_addr;
void (*pwrtest_entry)(unsigned,unsigned,unsigned,unsigned);
flush_cache_all();
addr = 0x1FF04400;
p_addr = (unsigned)virt_to_phys((void*)addr);
pwrtest_entry = (void (*)(unsigned,unsigned,unsigned,unsigned))p_addr;
if(test_flag != 1234){
test_flag = 1234;
printk("initial appf\n");
pwrtest_entry(APPF_INITIALIZE,0,0,0);
}
#ifdef CONFIG_SUSPEND_WATCHDOG
disable_watchdog();
#endif
printk("power down cpu --\n");
pwrtest_entry(APPF_POWER_DOWN_CPU,0,0,APPF_SAVE_PMU|APPF_SAVE_VFP|APPF_SAVE_L2);
#ifdef CONFIG_SUSPEND_WATCHDOG
enable_watchdog();
#endif
return 0;
}
static void aml_wdt_shutdown(struct platform_device *pdev)
{
struct watchdog_device *wdog = platform_get_drvdata(pdev);
struct aml_wdt_dev *wdev = watchdog_get_drvdata(wdog);
if (wdev->reset_watchdog_method == 1)
cancel_delayed_work(&wdev->boot_queue);
disable_watchdog(wdev);
}
static int aml_wtd_reboot_notify(struct notifier_block *nb,
unsigned long event,
void *dummy)
{
disable_watchdog(awdtv);
pr_info("disable watchdog\n");
return NOTIFY_OK;
}
static int aml_wdt_stop(struct watchdog_device *wdog)
{
struct aml_wdt_dev *wdev = watchdog_get_drvdata(wdog);
mutex_lock(&wdev->lock);
disable_watchdog(wdev);
mutex_unlock(&wdev->lock);
return 0;
}
static int aml_wdt_stop(struct watchdog_device *wdog)
{
spin_lock(&wdt_lock);
disable_watchdog();
spin_unlock(&wdt_lock);
return 0;
}
int main(int argc, char* argv[])
{
printf("payload compiled " __DATE__ " " __TIME__ "\n");
disable_watchdog(); printf("watchdog disabled.\n");
init_tcp();
init_usb();
printf("usbmux initialized\n");
return socket_listen();
}
ulg
decompress_kernel(ulg output_start, ulg free_mem_ptr_p, ulg free_mem_ptr_end_p)
{
output_data = (uch *) output_start;
free_mem_ptr = free_mem_ptr_p;
free_mem_ptr_end = free_mem_ptr_end_p;
disable_watchdog();
arch_decomp_setup();
/* initialize clock */
HAL_CLOCK_INITIALIZE(RTC_PERIOD);
printf("MicroRedBoot v1.4, (c) 2009 DD-WRT.COM (%s REVISION %s)\n", __DATE__,SVN_REVISION);
printf("keep the reset button pushed to enter redboot!\n");
printf("CPU Type: Atheros AR%s\n",get_system_type());
printf("CPU Clock: %dMhz\n", cpu_frequency() / 1000000);
nvram_init();
char *ddboard = nvram_get("DD_BOARD");
if (ddboard)
printf("Board: %s\n", ddboard);
char *resetbutton = nvram_get("resetbutton_enable");
if (resetbutton && !strcmp(resetbutton, "0"))
puts("reset button manual override detected! (nvram var resetbutton_enable=0)\n");
if (resetTouched() || (resetbutton && !strcmp(resetbutton, "0"))) {
puts("Reset Button triggered\nBooting Recovery RedBoot\n");
int count = 5;
while (count--) {
if (!resetTouched()) // check if reset button is unpressed again
break;
udelay(1000000);
}
if (count <= 0) {
puts("reset button 5 seconds pushed, erasing nvram\n");
if (!flashdetect())
flash_erase_nvram(flashsize, NVRAM_SPACE);
}
bootoffset = 0x800004bc;
resettrigger = 0;
puts("loading");
lzma_unzip();
puts("\n\n\n");
return output_ptr;
} else {
flashdetect();
linuxaddr = getLinux();
puts("Booting Linux\n");
resettrigger = 1;
/* important, enable ethernet bus, if the following lines are not initialized linux will not be able to use the ethernet mac, taken from redboot source */
enable_ethernet();
puts("loading");
lzma_unzip();
set_cmdline();
}
}
//-------------------------------------------------------------------
void notmain ( void )
{
disable_watchdog();
hexstring(0x12345678);
uart_string("Hello World!\r\n");
hexstring(0x12345678);
while(1)
{
uart_putc(uart_getc());
}
}
static int aml_wtd_pm_notify(struct notifier_block *nb, unsigned long event,
void *dummy)
{
if (event == PM_SUSPEND_PREPARE) {
disable_watchdog(awdtv);
pr_info("disable watchdog\n");
}
if (event == PM_POST_SUSPEND) {
enable_watchdog(awdtv);
pr_info("enable watchdog\n");
}
return NOTIFY_OK;
}
static void jtag_disable_watchdog(void)
{
switch (jtag_select) {
case AML_JTAG_AOPAD_AOCPU:
case AML_JTAG_AOPAD_SYSCPU:
case AML_JTAG_AOPAD_MEDIACPU:
case AML_JTAG_EEPAD_AOCPU:
case AML_JTAG_EEPAD_SYSCPU:
case AML_JTAG_EEPAD_MEDIACPU:
disable_watchdog();
break;
default:
break;
}
}
/**
* enter_state - Do common work of entering low-power state.
* @state: pm_state structure for state we're entering.
*
* Make sure we're the only ones trying to enter a sleep state. Fail
* if someone has beat us to it, since we don't want anything weird to
* happen when we wake up.
* Then, do the setup for suspend, enter the state, and cleaup (after
* we've woken up).
*/
int enter_state(suspend_state_t state)
{
int error;
if (!valid_state(state))
return -ENODEV;
if (!mutex_trylock(&pm_mutex))
return -EBUSY;
printk(KERN_INFO "PM: Syncing filesystems ... ");
sys_sync();
printk("done.\n");
pr_debug("PM: Preparing system for %s sleep\n", pm_states[state]);
error = suspend_prepare();
if (error){
printk(KERN_ERR "PM: suspend prepare failed ... ");
goto Unlock;
}
if (suspend_test(TEST_FREEZER)){
printk(KERN_ERR "PM: suspend test failed ... ");
goto Finish;
}
pr_debug("PM: Entering %s sleep\n", pm_states[state]);
error = suspend_devices_and_enter(state);
Finish:
pr_debug("PM: Finishing wakeup.\n");
suspend_finish();
Unlock:
mutex_unlock(&pm_mutex);
#ifdef CONFIG_SUSPEND_WATCHDOG
{
#ifdef CONFIG_HAS_EARLYSUSPEND
extern void reset_watchdog(void);
reset_watchdog();
#else
extern void disable_watchdog(void);
disable_watchdog();
#endif
}
#endif
return error;
}
void main(void) {
//volatile int i = 0;
//int flag = 1;
int i,j;
disable_watchdog();
init_modes_and_clock();
init_all();
initEMIOS_0Image();
init_fifoinit();
enable_irq();
//init_all_and_POST();
//g_f_enable_speed_control=1;
//write_camera_data_to_TF();
//set_speed_target(10);
//SetupBKL();
// SetupCCD();
//g_f_enable_speed_control=0;
//g_f_enable_supersonic=1;
//EMIOS_0.CH[3].CCR.B.FEN=1;//开场中断
//EMIOS_0.CH[7].CCR.B.FEN=1; //开行中断
// LCD_write_english_string(96,0,"T");
/* Loop forever */
for(;;)
{
//PGPDI
oe_enable();
readreset();
for(i=0;i<240;i++)
{
for(j=0;j<640;j++)
{
rck_high();
delay_us(150);
rck_low();
//delay_us(150);
}
}
}
/* Loop forever */
}
static noinline void imx53_guf_vincell_init(int is_lt)
{
void __iomem *ccm = (void *)MX53_CCM_BASE_ADDR;
void __iomem *uart = IOMEM(MX53_UART2_BASE_ADDR);
void *fdt;
u32 r;
enum bootsource src;
int instance;
arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8);
writel(0x0088494c, ccm + MX5_CCM_CBCDR);
writel(0x02b12f0a, ccm + MX5_CCM_CSCMR2);
imx53_ungate_all_peripherals();
imx53_init_lowlevel_early(800);
writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x27c);
writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x278);
imx53_uart_setup(uart);
pbl_set_putc(imx_uart_putc, uart);
pr_debug("GuF Vincell\n");
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
if (!(r > 0x70000000 && r < 0xf0000000)) {
disable_watchdog();
configure_dram_iomux();
imx_esdctlv4_init();
imx53_get_boot_source(&src, &instance);
if (src == BOOTSOURCE_NAND &&
IS_ENABLED(CONFIG_MACH_GUF_VINCELL_XLOAD))
imx53_nand_start_image();
}
if (is_lt)
fdt = __dtb_imx53_guf_vincell_lt_start;
else
fdt = __dtb_imx53_guf_vincell_start;
imx53_barebox_entry(fdt);
}
asmlinkage void car_stage_entry(void)
{
void *hob_list_ptr;
struct range_entry fsp_mem;
struct range_entry reg_car;
printk(BIOS_DEBUG, "Starting romstage...\n");
disable_watchdog();
soc_early_romstage_init();
/* Make sure the blob does not override our data in CAR */
range_entry_init(®_car, (uintptr_t)_car_relocatable_data_end,
(uintptr_t)_car_region_end, 0);
if (fsp_memory_init(&hob_list_ptr, ®_car) != FSP_SUCCESS) {
die("FSP memory init failed. Giving up.");
}
fsp_find_reserved_memory(&fsp_mem, hob_list_ptr);
/* initialize cbmem by adding FSP reserved memory first thing */
cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
range_entry_size(&fsp_mem));
/* make sure FSP memory is reserved in cbmem */
if (range_entry_base(&fsp_mem) !=
(uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY))
die("Failed to accommodate FSP reserved memory request");
/* Now that CBMEM is up, save the list so ramstage can use it */
fsp_save_hob_list(hob_list_ptr);
run_ramstage();
}
/*-----------------------------------------------------------------------*/
void init_all_and_POST(void)
{
int i = 0;
/* TF卡 */
TCHAR *path = "0:";
disable_watchdog();
init_modes_and_clock();
initEMIOS_0MotorAndSteer();
initEMIOS_0Image();/* 摄像头输入中断初始化 */
init_pit();
init_led();
init_DIP();
init_serial_port_0();
init_serial_port_1();
init_serial_port_2();
//init_ADC();
//init_serial_port_3();
init_supersonic_receive_0();
init_supersonic_receive_1();
// init_supersonic_receive_2();
// init_supersonic_receive_3();
init_supersonic_trigger_0();
init_supersonic_trigger_1();
// init_supersonic_trigger_2();
// init_supersonic_trigger_3();
// init_optical_encoder();
//init_DSPI_2();
//init_I2C();
init_choose_mode();
/* 初始化SPI总线 */
init_DSPI_1();
/* 开启外部总中断 */
enable_irq();
/* 初始化显示屏 */
initLCD();
//LCD_DISPLAY();
LCD_Fill(0xFF); /* 亮屏 */
delay_ms(50);
LCD_Fill(0x00); /* 黑屏 */
delay_ms(50);
#if 1
/* 初始化TF卡 */
LCD_P8x16Str(0,0, (BYTE*)"TF..");
if (!SD_init())
{
/* 挂载TF卡文件系统 */
if (FR_OK == f_mount(&fatfs1, path, 1))
{
/* 文件读写测试 */
if (!test_file_system())
{
g_devices_init_status.TFCard_is_OK = 1;
}
}
}
if (g_devices_init_status.TFCard_is_OK)
{
LCD_P8x16Str(0,0, (BYTE*)"TF..OK");
}
else
{
LCD_P8x16Str(0,0, (BYTE*)"TF..NOK");
suicide();
}
/* 读取设备号 */
LCD_P8x16Str(0, 4, (BYTE*)"DeviceNo=");
if (!read_device_no_from_TF())
{
if (WIFI_ADDRESS_WITHOUT_INIT != g_device_NO)
{
LCD_PrintoutInt(72, 4, g_device_NO);
}
else
{
suicide();
}
}
else
{
suicide();
}
/* 开启RFID读卡器主动模式 */
if (!init_RFID_modul_type())
{
g_devices_init_status.RFIDCard_energetic_mode_enable_is_OK = 1;
LCD_P8x16Str(0, 6, (BYTE*)"RFID..OK");
}
else
{
g_devices_init_status.RFIDCard_energetic_mode_enable_is_OK = 0;
LCD_P8x16Str(0, 6, (BYTE*)"RFID..NOK");
suicide();
}
delay_ms(1000);
/* 换屏 */
LCD_Fill(0x00);
/* 读取舵机参数 */
LCD_P8x16Str(0, 0, (BYTE*)"StH.L=");
if (read_steer_helm_data_from_TF())
{
suicide();
}
update_steer_helm_basement_to_steer_helm();
LCD_PrintoutInt(48, 0, data_steer_helm_basement.left_limit);
set_steer_helm_basement(data_steer_helm_basement.left_limit);
delay_ms(500);
LCD_P8x16Str(0, 2, (BYTE*)"StH.R=");
LCD_PrintoutInt(48, 2, data_steer_helm_basement.right_limit);
set_steer_helm_basement(data_steer_helm_basement.right_limit);
delay_ms(500);
LCD_P8x16Str(0, 4, (BYTE*)"StH.C=");
LCD_PrintoutInt(48, 4, data_steer_helm_basement.center);
set_steer_helm_basement(data_steer_helm_basement.center);
/* 读取mode号 */
LCD_P8x16Str(0, 6, (BYTE*)"MODE=");
LCD_PrintoutInt(40, 6, mode);
//set_pos_target();
delay_ms(1000);
/* 换屏 */
LCD_Fill(0x00);
/* 速度闭环测试 */
g_f_enable_speed_control = 1;
LCD_P8x16Str(0, 4, (BYTE*)"S.T=0");
set_speed_target(0);
delay_ms(2000);
/* 换屏 */
LCD_Fill(0x00);
#endif
}
static int __init aml_wdt_driver_init(void)
{
printk("%s,%d\n",__func__,__LINE__);
disable_watchdog();
return platform_driver_register(&(aml_wdt_driver));
}
/*-----------------------------------------------------------------------*/
void init_all_and_POST(void)
{
int i = 0;
disable_watchdog();
init_modes_and_clock();
initEMIOS_0MotorAndSteer();
/* PIT：光编读值&速度控制 */
// init_pit_10ms();
/* PIT：步进电机控制&角度控制标志位 */
init_pit_1ms();
//init_Stepmotor(); /* 初始化步进电机 */
init_led();
//init_DIP(); /* 拨码开关 */
init_serial_port_1(); /* BlueTooth */
init_ADC(); /* 陀螺仪读值 - 其中一路ADC与MPU9250片选冲突，不要同时打开*/
init_optical_encoder(); /* 光编 */
//init_I2C();
//init_choose_mode(); /* 拨码开关模式选择 */
/* 初始化SPI总线 */
init_DSPI_1();
/* 开启外部总中断 */
enable_irq();
/* 初始化显示屏 */
initLCD();
LCD_DISPLAY();
LCD_Fill(0xFF); /* 亮屏 */
delay_ms(50);
LCD_Fill(0x00); /* 黑屏 */
delay_ms(50);
/*初始化螺旋桨电机，给1000占空比*/
set_PropellerA_motor_pwm(1000);
set_PropellerB_motor_pwm(1000);
/* 初始化TF卡 */
//test_init_TF();
/* 读取设备号 */
//read_device_no();
/* 初始化陀螺仪 */
// init_MPU9250();
//delay_ms(1000);
/* 换屏 */
//LCD_Fill(0x00);
/* 读取舵机参数 */
//read_display_helm();
/* 读取拨码开关模式号 */
//read_DIP_mode();
//delay_ms(1000);
/* 换屏 */
//LCD_Fill(0x00);
/* 速度闭环开启及测试 速度=0 */
//init_speed_control();
// g_f_enable_supersonic=1;
//delay_ms(2000);
/* 换屏 */
//LCD_Fill(0x00);
}
asmlinkage void car_stage_entry(void)
{
void *hob_list_ptr;
const void *mrc_data;
struct range_entry fsp_mem, reg_car;
struct postcar_frame pcf;
size_t mrc_data_size;
uintptr_t top_of_ram;
int prev_sleep_state;
struct romstage_handoff *handoff;
struct chipset_power_state *ps = car_get_var_ptr(&power_state);
timestamp_add_now(TS_START_ROMSTAGE);
soc_early_romstage_init();
disable_watchdog();
console_init();
prev_sleep_state = fill_power_state(ps);
/* Make sure the blob does not override our data in CAR */
range_entry_init(®_car, (uintptr_t)_car_relocatable_data_end,
(uintptr_t)_car_region_end, 0);
if (fsp_memory_init(&hob_list_ptr, ®_car) != FSP_SUCCESS) {
die("FSP memory init failed. Giving up.");
}
fsp_find_reserved_memory(&fsp_mem, hob_list_ptr);
/* initialize cbmem by adding FSP reserved memory first thing */
if (prev_sleep_state != SLEEP_STATE_S3) {
cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
range_entry_size(&fsp_mem));
} else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
range_entry_size(&fsp_mem))) {
if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
/* Failed S3 resume, reset to come up cleanly */
hard_reset();
}
}
/* make sure FSP memory is reserved in cbmem */
if (range_entry_base(&fsp_mem) !=
(uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY))
die("Failed to accommodate FSP reserved memory request");
/* Now that CBMEM is up, save the list so ramstage can use it */
fsp_save_hob_list(hob_list_ptr);
/* Save MRC Data to CBMEM */
if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS) &&
(prev_sleep_state != SLEEP_STATE_S3))
{
mrc_data = fsp_find_nv_storage_data(&mrc_data_size);
if (mrc_data && mrc_cache_stash_data(mrc_data, mrc_data_size) < 0)
printk(BIOS_ERR, "Failed to stash MRC data\n");
}
/* Create romstage handof information */
handoff = romstage_handoff_find_or_add();
if (handoff != NULL)
handoff->s3_resume = (prev_sleep_state == SLEEP_STATE_S3);
else
printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
if (postcar_frame_init(&pcf, 1*KiB))
die("Unable to initialize postcar frame.\n");
/*
* We need to make sure ramstage will be run cached. At this point exact
* location of ramstage in cbmem is not known. Instruct postcar to cache
* 16 megs under cbmem top which is a safe bet to cover ramstage.
*/
top_of_ram = (uintptr_t) cbmem_top();
/* cbmem_top() needs to be at least 16 MiB aligned */
assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram);
postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK);
run_postcar_phase(&pcf);
}
asmlinkage void car_stage_entry(void)
{
struct postcar_frame pcf;
uintptr_t top_of_ram;
bool s3wake;
struct chipset_power_state *ps = car_get_var_ptr(&power_state);
void *smm_base;
size_t smm_size, var_size;
const void *new_var_data;
uintptr_t tseg_base;
timestamp_add_now(TS_START_ROMSTAGE);
soc_early_romstage_init();
disable_watchdog();
console_init();
s3wake = fill_power_state(ps) == ACPI_S3;
fsp_memory_init(s3wake);
if (punit_init())
set_max_freq();
else
printk(BIOS_DEBUG, "Punit failed to initialize properly\n");
/* Stash variable MRC data and let cache system update it later */
new_var_data = fsp_find_extension_hob_by_guid(hob_variable_guid,
&var_size);
if (new_var_data)
mrc_cache_stash_vardata(new_var_data, var_size,
car_get_var(fsp_version));
else
printk(BIOS_ERR, "Failed to determine variable data\n");
if (postcar_frame_init(&pcf, 1*KiB))
die("Unable to initialize postcar frame.\n");
mainboard_save_dimm_info();
/*
* We need to make sure ramstage will be run cached. At this point exact
* location of ramstage in cbmem is not known. Instruct postcar to cache
* 16 megs under cbmem top which is a safe bet to cover ramstage.
*/
top_of_ram = (uintptr_t) cbmem_top();
/* cbmem_top() needs to be at least 16 MiB aligned */
assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram);
postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK);
/* Cache the memory-mapped boot media. */
if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))
postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE,
MTRR_TYPE_WRPROT);
/*
* Cache the TSEG region at the top of ram. This region is
* not restricted to SMM mode until SMM has been relocated.
* By setting the region to cacheable it provides faster access
* when relocating the SMM handler as well as using the TSEG
* region for other purposes.
*/
smm_region(&smm_base, &smm_size);
tseg_base = (uintptr_t)smm_base;
postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK);
run_postcar_phase(&pcf);
}
