static int ovl_layer_config(DISP_MODULE_ENUM module,
unsigned int layer,
unsigned int source,
DpColorFormat format,
unsigned long addr,
unsigned int src_x, /* ROI x offset*/
unsigned int src_y, /* ROI y offset*/
unsigned int src_pitch,
unsigned int dst_x, /* ROI x offset*/
unsigned int dst_y, /* ROI y offset*/
unsigned int dst_w, /* ROT width*/
unsigned int dst_h, /* ROI height*/
unsigned int key_en,
unsigned int key, /*color key*/
unsigned int aen, /* alpha enable*/
unsigned char alpha,
unsigned int sur_aen,
unsigned int src_alpha,
unsigned int dst_alpha,
unsigned int constant_color,
unsigned int yuv_range,
DISP_BUFFER_TYPE sec,
unsigned int is_engine_sec,
void *handle)
{
int idx = ovl_index(module);
unsigned int value = 0;
enum OVL_INPUT_FORMAT fmt = ovl_input_fmt_convert(format);
unsigned int bpp = ovl_input_fmt_bpp(fmt);
unsigned int input_swap = ovl_input_fmt_byte_swap(fmt);
unsigned int input_fmt = ovl_input_fmt_reg_value(fmt);
enum OVL_COLOR_SPACE space = ovl_input_fmt_color_space(fmt);
unsigned int offset = 0;
/*0100 MTX_JPEG_TO_RGB (YUV FUll TO RGB)*/
int color_matrix = 0x4;
unsigned int idx_offset = idx*DISP_OVL_INDEX_OFFSET;
unsigned int layer_offset = idx_offset + layer * OVL_LAYER_OFFSET;
#ifdef CONFIG_MTK_LCM_PHYSICAL_ROTATION_HW
unsigned int bg_h, bg_w;
#endif
switch(yuv_range)
{
case 0: color_matrix = 4; break; //BT601_full
case 1: color_matrix = 6; break; //BT601
case 2: color_matrix = 7; break; //BT709
default:
DDPERR("un-recognized yuv_range=%d! \n", yuv_range);
color_matrix = 4;
}
// DDPMSG("color matrix=%d. \n", color_matrix);
ASSERT((dst_w <= OVL_MAX_WIDTH) &&
(dst_h <= OVL_MAX_HEIGHT) &&
(layer <= 3));
if (addr == 0) {
DDPERR("source from memory, but addr is 0!\n");
ASSERT(0);
}
#if defined(CONFIG_TRUSTONIC_TEE_SUPPORT) && defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
DDPMSG("ovl%d, layer=%d, source=%s, off(x=%d, y=%d), dst(%d, %d, %d, %d),pitch=%d,"
"fmt=%s, addr=%lx, keyEn=%d, key=%d, aen=%d, alpha=%d,"
"sur_aen=%d,sur_alpha=0x%x, constant_color=0x%x, yuv_range=%d, sec=%d,ovlsec=%d\n",
idx, layer, (source==0)?"memory":"dim", src_x, src_y,dst_x, dst_y,
dst_w, dst_h, src_pitch, ovl_intput_format_name(fmt, input_swap),
addr, key_en, key, aen, alpha, sur_aen,
dst_alpha<<2 | src_alpha, constant_color, yuv_range, sec, is_engine_sec);
#endif
if(source==OVL_LAYER_SOURCE_RESERVED) //==1, means constant color
{
if(aen==0)
{
DDPERR("dim layer ahpha enable should be 1!\n");
}
if(fmt!=OVL_INPUT_FORMAT_RGB565 && fmt!=OVL_INPUT_FORMAT_RGB888)
{
//DDPERR("dim layer format should be RGB565");
fmt = OVL_INPUT_FORMAT_RGB888;
input_fmt = ovl_input_fmt_reg_value(fmt);
}
}
// DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_RDMA0_CTRL+layer_offset, 0x1);
value = (REG_FLD_VAL((L_CON_FLD_LARC), (source)) |
REG_FLD_VAL((L_CON_FLD_CFMT), (input_fmt)) |
REG_FLD_VAL((L_CON_FLD_AEN), (aen)) |
REG_FLD_VAL((L_CON_FLD_APHA), (alpha)) |
REG_FLD_VAL((L_CON_FLD_SKEN), (key_en)) |
REG_FLD_VAL((L_CON_FLD_BTSW), (input_swap)));
if (space == OVL_COLOR_SPACE_YUV)
value = value | REG_FLD_VAL((L_CON_FLD_MTX), (color_matrix));
#ifdef CONFIG_MTK_LCM_PHYSICAL_ROTATION_HW
value |= 0x600;
#endif
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_CON+layer_offset, value);
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_CLR+idx_offset+layer*4, constant_color);
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_SRC_SIZE+layer_offset,
dst_h<<16 | dst_w);
#ifdef CONFIG_MTK_LCM_PHYSICAL_ROTATION_HW
bg_h = DISP_REG_GET(idx_offset + DISP_REG_OVL_ROI_SIZE);
bg_w = bg_h & 0xFFFF;
bg_h = bg_h >> 16;
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_OFFSET+layer_offset, ((bg_h-dst_h-dst_y)<<16)|(bg_w-dst_w-dst_x));
#else
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_OFFSET+layer_offset,
dst_y<<16 | dst_x);
#endif
#ifdef CONFIG_MTK_LCM_PHYSICAL_ROTATION_HW
offset = src_pitch*(dst_h+src_y-1)+(src_x+dst_w)*bpp-1;
#else
offset = src_x*bpp+src_y*src_pitch;
#endif
if(!is_engine_sec) {
DISP_REG_SET(handle, DISP_REG_OVL_L0_ADDR+layer_offset, addr+offset);
} else {
unsigned int size;
int m4u_port;
size = (dst_h-1)*src_pitch + dst_w*bpp;
#if defined(MTK_FB_OVL1_SUPPORT)
m4u_port = idx==0 ? M4U_PORT_DISP_OVL0 : M4U_PORT_DISP_OVL1;
#else
m4u_port = M4U_PORT_DISP_OVL0;
#endif
if(sec != DISP_SECURE_BUFFER) {
/* ovl is sec but this layer is non-sec */
/* we need to tell cmdq to help map non-sec mva to sec mva */
cmdqRecWriteSecure(handle, disp_addr_convert(DISP_REG_OVL_L0_ADDR+layer_offset),
CMDQ_SAM_NMVA_2_MVA, addr+offset, 0, size, m4u_port);
} else {
/* for sec layer, addr variable stores sec handle*/
/* we need to pass this handle and offset to cmdq driver */
/* cmdq sec driver will help to convert handle to correct address */
offset = src_x*bpp+src_y*src_pitch;
cmdqRecWriteSecure(handle, disp_addr_convert(DISP_REG_OVL_L0_ADDR+layer_offset),
CMDQ_SAM_H_2_MVA, addr, offset, size, m4u_port);
}
}
if(key_en==1)
{
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_SRCKEY+layer_offset, key);
}
value = (((sur_aen & 0x1) << 15) |
((dst_alpha & 0x3) << 6) | ((dst_alpha & 0x3) << 4) |
((src_alpha & 0x3)<<2) | (src_alpha & 0x3));
value = (REG_FLD_VAL((L_PITCH_FLD_SUR_ALFA), (value)) |
REG_FLD_VAL((L_PITCH_FLD_LSP), (src_pitch)));
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_PITCH+layer_offset, value);
if(idx==0)
{
if(primary_display_is_decouple_mode()==0)
{
if(DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset)!=0x6070)
DISP_REG_SET(handle, DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset, 0x6070);
}
else
{
if(DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset)!=0x50FF)
DISP_REG_SET(handle, DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset, 0x50FF);
}
}
if(idx==1)
{
if(primary_display_is_decouple_mode()==0 && ovl_get_status()!=DDP_OVL1_STATUS_SUB)
{
if(DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset)!=0x6070)
DISP_REG_SET(handle, DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset, 0x6070);
}
else
{
if(DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset)!=0x50FF)
DISP_REG_SET(handle, DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset, 0x50FF);
}
}
return 0;
}
static int rdma_config(DISP_MODULE_ENUM module,
enum RDMA_MODE mode,
unsigned long address,
DpColorFormat inFormat,
unsigned pitch,
unsigned width,
unsigned height,
unsigned ufoe_enable,
DISP_BUFFER_TYPE sec,
void * handle)
{
unsigned int output_is_yuv = 0;
enum RDMA_INPUT_FORMAT inputFormat = rdma_input_format_convert(inFormat);
unsigned int bpp = rdma_input_format_bpp(inputFormat);
unsigned int input_is_yuv = rdma_input_format_color_space(inputFormat);
unsigned int input_swap = rdma_input_format_byte_swap(inputFormat);
unsigned int input_format_reg = rdma_input_format_reg_value(inputFormat);
unsigned int color_matrix = 0x4; //0100 MTX_JPEG_TO_RGB (YUV FUll TO RGB)
unsigned int idx = rdma_index(module);
#if defined(CONFIG_TRUSTONIC_TEE_SUPPORT) && defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
DDPMSG("RDMAConfig idx %d, mode %d, address 0x%lx, inputformat %s, pitch %u, width %u, height %u,sec%d\n",
idx, mode, address, rdma_intput_format_name(inputFormat,input_swap), pitch,width, height, sec);
#else
DDPDBG("RDMAConfig idx %d, mode %d, address 0x%lx, inputformat %s, pitch %u, width %u, height %u,sec%d\n",
idx, mode, address, rdma_intput_format_name(inputFormat,input_swap), pitch,width, height, sec);
#endif
ASSERT(idx <= 2);
if((width > RDMA_MAX_WIDTH) || (height > RDMA_MAX_HEIGHT))
{
DDPERR("RDMA input overflow, w=%d, h=%d, max_w=%d, max_h=%d\n", width, height, RDMA_MAX_WIDTH, RDMA_MAX_HEIGHT);
}
if(input_is_yuv==1 && output_is_yuv==0)
{
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_MATRIX_ENABLE, idx * DISP_RDMA_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, 1);
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_MATRIX_INT_MTX_SEL, idx * DISP_RDMA_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, color_matrix);
}
else if(input_is_yuv==0 && output_is_yuv==1)
{
color_matrix = 0x2; //0x0010, RGB_TO_BT601
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_MATRIX_ENABLE, idx * DISP_RDMA_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, 1);
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_MATRIX_INT_MTX_SEL, idx * DISP_RDMA_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, color_matrix);
}
else
{
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_MATRIX_ENABLE, idx * DISP_RDMA_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, 0);
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_MATRIX_INT_MTX_SEL, idx * DISP_RDMA_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, 0);
}
DISP_REG_SET_FIELD(handle,GLOBAL_CON_FLD_MODE_SEL, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_GLOBAL_CON, mode);
// FORMAT & SWAP only works when RDMA memory mode, set both to 0 when RDMA direct link mode.
DISP_REG_SET_FIELD(handle,MEM_CON_FLD_MEM_MODE_INPUT_FORMAT, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_MEM_CON, ((mode == RDMA_MODE_DIRECT_LINK) ? 0 : input_format_reg&0xf));
DISP_REG_SET_FIELD(handle,MEM_CON_FLD_MEM_MODE_INPUT_SWAP, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_MEM_CON, ((mode == RDMA_MODE_DIRECT_LINK) ? 0 : input_swap));
if(sec != DISP_SECURE_BUFFER) {
DISP_REG_SET(handle,idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_MEM_START_ADDR, address);
} else {
int m4u_port;
unsigned int size = pitch * height;
m4u_port = idx==0 ? M4U_PORT_DISP_RDMA0 : M4U_PORT_DISP_RDMA1;
/* for sec layer, addr variable stores sec handle*/
/* we need to pass this handle and offset to cmdq driver */
/* cmdq sec driver will help to convert handle to correct address */
cmdqRecWriteSecure(handle, disp_addr_convert(idx*DISP_RDMA_INDEX_OFFSET+DISP_REG_RDMA_MEM_START_ADDR),
CMDQ_SAM_H_2_MVA, address, 0, size, m4u_port);
//DISP_REG_SET(handle,idx*DISP_RDMA_INDEX_OFFSET+DISP_REG_RDMA_MEM_START_ADDR, address-0xbc000000+0x8c00000);
}
DISP_REG_SET(handle,idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_MEM_SRC_PITCH, pitch);
//DISP_REG_SET(handle,idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_INT_ENABLE, 0x3F);
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_OUTPUT_FRAME_WIDTH, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_SIZE_CON_0, width);
DISP_REG_SET_FIELD(handle,SIZE_CON_1_FLD_OUTPUT_FRAME_HEIGHT, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_SIZE_CON_1, height);
rdma_set_ultra(idx, width, height, bpp, rdma_fps[idx], handle);
#if 1
if(0) //UFOE bypassed, enable RDMA underflow intr, else disable RDMA underflow intr
{
DISP_REG_SET_FIELD(handle,FIFO_CON_FLD_FIFO_UNDERFLOW_EN, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_FIFO_CON, 1);
DISP_REG_SET_FIELD(handle,FIFO_CON_FLD_OUTPUT_VALID_FIFO_THRESHOLD, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_FIFO_CON, gRDMAFIFOLen);
}
else
{
DISP_REG_SET_FIELD(handle,FIFO_CON_FLD_FIFO_UNDERFLOW_EN, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_FIFO_CON, 1);
DISP_REG_SET_FIELD(handle,FIFO_CON_FLD_OUTPUT_VALID_FIFO_THRESHOLD, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_FIFO_CON, width*3*3/16/2); //FHD:304, HD:203, QHD:151
}
#endif
return 0;
}
static int wdma_config(DISP_MODULE_ENUM module,
unsigned srcWidth,
unsigned srcHeight,
unsigned clipX,
unsigned clipY,
unsigned clipWidth,
unsigned clipHeight,
DpColorFormat out_format,
unsigned long dstAddress,
unsigned dstPitch,
unsigned int useSpecifiedAlpha,
unsigned char alpha,
DISP_BUFFER_TYPE sec,
void * handle)
{
unsigned int idx = wdma_index(module);
unsigned int output_swap = fmt_swap(out_format);
unsigned int output_color_space = fmt_color_space(out_format);
unsigned int out_fmt_reg = fmt_hw_value(out_format);
unsigned int yuv444_to_yuv422 = 0;
int color_matrix = 0x2; //0010 RGB_TO_BT601
unsigned int idx_offst = idx*DISP_WDMA_INDEX_OFFSET;
size_t size = dstPitch * clipHeight;
#if defined(CONFIG_TRUSTONIC_TEE_SUPPORT) && defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
DDPMSG("module %s, src(w=%d,h=%d), clip(x=%d,y=%d,w=%d,h=%d),out_fmt=%s,dst_address=0x%lx,dst_p=%d,spific_alfa=%d,alpa=%d,handle=0x%p,sec%d\n",
ddp_get_module_name(module),srcWidth,srcHeight,
clipX,clipY,clipWidth,clipHeight,
fmt_string(out_format),dstAddress,dstPitch,
useSpecifiedAlpha,alpha,handle,sec);
#endif
// should use OVL alpha instead of sw config
DISP_REG_SET(handle,idx_offst+DISP_REG_WDMA_SRC_SIZE, srcHeight<<16 | srcWidth);
DISP_REG_SET(handle,idx_offst+DISP_REG_WDMA_CLIP_COORD, clipY<<16 | clipX);
DISP_REG_SET(handle,idx_offst+DISP_REG_WDMA_CLIP_SIZE, clipHeight<<16 | clipWidth);
DISP_REG_SET_FIELD(handle,CFG_FLD_OUT_FORMAT,idx_offst+DISP_REG_WDMA_CFG, out_fmt_reg);
if(output_color_space == WDMA_COLOR_SPACE_YUV) {
yuv444_to_yuv422 = fmt_is_yuv422(out_format);
// set DNSP for UYVY and YUV_3P format for better quality
DISP_REG_SET_FIELD(handle,CFG_FLD_DNSP_SEL, idx_offst+DISP_REG_WDMA_CFG, yuv444_to_yuv422);
if(fmt_is_yuv420(out_format))
{
wdma_config_yuv420(module,out_format,dstPitch,clipHeight,dstAddress,sec,handle);
}
/*user internal matrix*/
DISP_REG_SET_FIELD(handle,CFG_FLD_EXT_MTX_EN, idx_offst+DISP_REG_WDMA_CFG, 0);
DISP_REG_SET_FIELD(handle,CFG_FLD_CT_EN, idx_offst+DISP_REG_WDMA_CFG, 1);
DISP_REG_SET_FIELD(handle,CFG_FLD_INT_MTX_SEL, idx_offst+DISP_REG_WDMA_CFG, color_matrix);
}
else
{
DISP_REG_SET_FIELD(handle,CFG_FLD_EXT_MTX_EN, idx_offst+DISP_REG_WDMA_CFG, 0);
DISP_REG_SET_FIELD(handle,CFG_FLD_CT_EN, idx_offst+DISP_REG_WDMA_CFG, 0);
}
DISP_REG_SET_FIELD(handle,CFG_FLD_SWAP, idx_offst+DISP_REG_WDMA_CFG, output_swap);
if(sec != DISP_SECURE_BUFFER) {
DISP_REG_SET(handle, idx_offst+DISP_REG_WDMA_DST_ADDR0, dstAddress);
} else {
int m4u_port;
m4u_port = M4U_PORT_DISP_WDMA0;
/* for sec layer, addr variable stores sec handle*/
/* we need to pass this handle and offset to cmdq driver */
/* cmdq sec driver will help to convert handle to correct address */
cmdqRecWriteSecure(handle, disp_addr_convert(idx_offst+DISP_REG_WDMA_DST_ADDR0),
CMDQ_SAM_H_2_MVA, dstAddress, 0, size, m4u_port);
}
DISP_REG_SET(handle, idx_offst+DISP_REG_WDMA_DST_W_IN_BYTE, dstPitch);
DISP_REG_SET_FIELD(handle,ALPHA_FLD_A_SEL, idx_offst+DISP_REG_WDMA_ALPHA, useSpecifiedAlpha);
DISP_REG_SET_FIELD(handle,ALPHA_FLD_A_VALUE, idx_offst+DISP_REG_WDMA_ALPHA, alpha);
wdma_calc_ultra(idx, srcWidth, srcHeight, 6, 60, handle);
return 0;
}
static int wdma_config_l(DISP_MODULE_ENUM module, disp_ddp_path_config* pConfig, void *handle)
{
WDMA_CONFIG_STRUCT* config = &pConfig->wdma_config;
int wdma_idx = wdma_index(module);
CMDQ_ENG_ENUM cmdq_engine;
if (!pConfig->wdma_dirty) {
return 0;
}
//warm reset wdma every time we use it
if(handle) {
if(/*(primary_display_is_video_mode()==0 && primary_display_is_decouple_mode()==0) ||*/
primary_display_is_decouple_mode()==1)
{
unsigned int idx_offst = wdma_idx*DISP_WDMA_INDEX_OFFSET;
DISP_REG_SET(handle, idx_offst+DISP_REG_WDMA_RST, 0x01); // trigger soft reset
cmdqRecPoll(handle, disp_addr_convert(idx_offst+DISP_REG_WDMA_FLOW_CTRL_DBG), 1, 0x1);
DISP_REG_SET(handle, idx_offst+DISP_REG_WDMA_RST , 0x0); // trigger soft reset
}
}
cmdq_engine = wdma_idx==0 ? CMDQ_ENG_DISP_WDMA0 : CMDQ_ENG_DISP_WDMA1;
if(config->security == DISP_SECURE_BUFFER) {
cmdqRecSetSecure(handle, 1);
/* set engine as sec */
cmdqRecSecureEnablePortSecurity(handle, (1LL << cmdq_engine));
cmdqRecSecureEnableDAPC(handle, (1LL << cmdq_engine));
if(wdma_is_sec[wdma_idx] == 0)
DDPMSG("[SVP] switch wdma%d to sec\n", wdma_idx);
wdma_is_sec[wdma_idx] = 1;
} else {
if(wdma_is_sec[wdma_idx]) {
/* wdma is in sec stat, we need to switch it to nonsec */
cmdqRecHandle nonsec_switch_handle;
int ret;
ret = cmdqRecCreate(CMDQ_SCENARIO_DISP_PRIMARY_DISABLE_SECURE_PATH, &(nonsec_switch_handle));
if(ret)
DDPAEE("[SVP]fail to create disable handle %s ret=%d\n", __FUNCTION__, ret);
cmdqRecReset(nonsec_switch_handle);
_cmdq_insert_wait_frame_done_token_mira(nonsec_switch_handle);
cmdqRecSetSecure(nonsec_switch_handle, 1);
/*in fact, dapc/port_sec will be disabled by cmdq*/
cmdqRecSecureEnablePortSecurity(nonsec_switch_handle, (1LL << cmdq_engine));
cmdqRecSecureEnableDAPC(nonsec_switch_handle, (1LL << cmdq_engine));
cmdqRecFlushAsync(nonsec_switch_handle);
cmdqRecDestroy(nonsec_switch_handle);
DDPMSG("[SVP] switch wdma%d to nonsec\n", wdma_idx);
}
wdma_is_sec[wdma_idx] = 0;
}
if (wdma_check_input_param(config) == 0)
wdma_config(module,
config->srcWidth,
config->srcHeight,
config->clipX,
config->clipY,
config->clipWidth,
config->clipHeight,
config->outputFormat,
config->dstAddress,
config->dstPitch,
config->useSpecifiedAlpha,
config->alpha,
config->security,
handle);
return 0;
}
static int wdma_config_yuv420(DISP_MODULE_ENUM module,
DpColorFormat fmt,
unsigned int dstPitch,
unsigned int Height,
unsigned long dstAddress,
DISP_BUFFER_TYPE sec,
void * handle)
{
unsigned int idx = wdma_index(module);
unsigned int idx_offst = idx*DISP_WDMA_INDEX_OFFSET;
size_t size;
unsigned int u_off = 0;
unsigned int v_off = 0;
unsigned int u_stride = 0;
unsigned int y_size = 0;
unsigned int u_size = 0;
unsigned int v_size = 0;
unsigned int stride = dstPitch;
int has_v = 1;
if(fmt == eYV12)
{
y_size = stride * Height;
u_stride = ALIGN_TO(stride/2,16);
u_size = u_stride * Height/2;
u_off = y_size;
v_off = y_size + u_size;
}
else if(fmt == eYV21)
{
y_size = stride * Height;
u_stride = ALIGN_TO(stride/2,16);
u_size = u_stride * Height/2;
u_off = y_size;
v_off = y_size + u_size;
}
else if(fmt == eNV12 || fmt == eNV21)
{
y_size = stride * Height;
u_stride = stride/2;
u_size = u_stride * Height/2;
u_off = y_size;
has_v = 0;
}
if(sec != DISP_SECURE_BUFFER) {
DISP_REG_SET(handle,idx_offst+DISP_REG_WDMA_DST_ADDR1, dstAddress + u_off);
if(has_v)
DISP_REG_SET(handle,idx_offst+DISP_REG_WDMA_DST_ADDR2, dstAddress + v_off);
} else {
int m4u_port;
m4u_port = M4U_PORT_DISP_WDMA0;
cmdqRecWriteSecure(handle, disp_addr_convert(idx_offst+DISP_REG_WDMA_DST_ADDR1),
CMDQ_SAM_H_2_MVA, dstAddress, u_off, u_size, m4u_port);
if(has_v)
cmdqRecWriteSecure(handle, disp_addr_convert(idx_offst+DISP_REG_WDMA_DST_ADDR2),
CMDQ_SAM_H_2_MVA, dstAddress, v_off, u_size, m4u_port);
}
DISP_REG_SET_FIELD(handle,DST_W_IN_BYTE_FLD_DST_W_IN_BYTE, idx_offst+DISP_REG_WDMA_DST_UV_PITCH, u_stride);
return 0;
}