static s32 vdevice_clk_config(struct disp_device *vdevice)
{
struct disp_vdevice_private_data *vdevicep = disp_vdevice_get_priv(vdevice);
disp_panel_para *para;
struct lcd_clk_info clk_info;
unsigned long pll_rate, lcd_rate, dclk_rate;//hz
unsigned long pll_rate_set, lcd_rate_set, dclk_rate_set;//hz
if(!vdevice || !vdevicep) {
DE_WRN("null hdl!\n");
return DIS_FAIL;
}
memset(&clk_info, 0, sizeof(struct lcd_clk_info));
para = (disp_panel_para*)disp_sys_malloc(sizeof(disp_panel_para));
dclk_rate = vdevicep->video_info->pixel_clk * (vdevicep->video_info->pixel_repeat + 1);
para->lcd_if = vdevicep->intf.intf;
para->lcd_dclk_freq = dclk_rate;
disp_al_lcd_get_clk_info(vdevice->disp, &clk_info, para);
disp_sys_free((void*)para);
clk_info.tcon_div = 8;//fixme
lcd_rate = dclk_rate * clk_info.tcon_div;
pll_rate = lcd_rate * clk_info.lcd_div;
disp_sys_clk_set_rate(vdevicep->clk_parent, pll_rate);
pll_rate_set = disp_sys_clk_get_rate(vdevicep->clk_parent);
lcd_rate_set = pll_rate_set / clk_info.lcd_div;
disp_sys_clk_set_rate(vdevicep->clk, lcd_rate_set);
lcd_rate_set = disp_sys_clk_get_rate(vdevicep->clk);
dclk_rate_set = lcd_rate_set / clk_info.tcon_div;
if(dclk_rate_set != dclk_rate)
DE_WRN("pclk=%ld, cur=%ld\n", dclk_rate, dclk_rate_set);
return 0;
}
int disp_al_lcd_cfg(u32 screen_id, disp_panel_para * panel, panel_extend_para *extend_panel)
{
struct lcd_clk_info info;
al_priv.output_type[screen_id] = (u32)DISP_OUTPUT_TYPE_LCD;
al_priv.output_type[screen_id] = (u32)panel->lcd_if;
tcon_init(screen_id);
disp_al_lcd_get_clk_info(screen_id, &info, panel);
tcon0_set_dclk_div(screen_id, info.tcon_div);
if(0 != tcon0_cfg(screen_id, panel))
DE_WRN("lcd cfg fail!\n");
else
DE_INF("lcd cfg ok!\n");
tcon0_cfg_ext(screen_id, extend_panel);
if(LCD_IF_DSI == panel->lcd_if) {
#if defined(SUPPORT_DSI)
if(0 != dsi_cfg(screen_id, panel)) {
DE_WRN("dsi cfg fail!\n");
}
#endif
}
return 0;
}
int disp_al_vdevice_cfg(u32 screen_id, disp_video_timings *video_info, disp_vdevice_interface_para *para)
{
struct lcd_clk_info clk_info;
disp_panel_para info;
al_priv.output_type[screen_id] = (u32)DISP_OUTPUT_TYPE_LCD;
al_priv.output_mode[screen_id] = (u32)para->intf;
memset(&info, 0, sizeof(disp_panel_para));
info.lcd_if = para->intf;
info.lcd_x = video_info->x_res;
info.lcd_y = video_info->y_res;
info.lcd_hv_if = (disp_lcd_hv_if)para->sub_intf;
info.lcd_dclk_freq = video_info->pixel_clk;
info.lcd_ht = video_info->hor_total_time;
info.lcd_hbp = video_info->hor_back_porch + video_info->hor_sync_time;
info.lcd_hspw = video_info->hor_sync_time;
info.lcd_vt = video_info->ver_total_time;
info.lcd_vbp = video_info->ver_back_porch + video_info->ver_sync_time;
info.lcd_vspw = video_info->ver_sync_time;
info.lcd_hv_syuv_fdly = para->fdelay;
if(LCD_HV_IF_CCIR656_2CYC == info.lcd_hv_if)
info.lcd_hv_syuv_seq = para->sequence;
else
info.lcd_hv_srgb_seq = para->sequence;
tcon_init(screen_id);
disp_al_lcd_get_clk_info(screen_id, &clk_info, &info);
clk_info.tcon_div = 11;//fixme
tcon0_set_dclk_div(screen_id, clk_info.tcon_div);
if(0 != tcon0_cfg(screen_id, &info))
DE_WRN("lcd cfg fail!\n");
else
DE_INF("lcd cfg ok!\n");
return 0;
}
int disp_al_lcd_cfg(u32 screen_id, disp_panel_para * panel)
{
struct lcd_clk_info info;
tcon_init(screen_id);
disp_al_lcd_get_clk_info(screen_id, &info, panel);
DE_INF("lcd %d clk_div=%d!\n", screen_id, info.tcon_div);
tcon0_set_dclk_div(screen_id, info.tcon_div);
if(0 != tcon0_cfg(screen_id, panel))
DE_WRN("lcd cfg fail!\n");
else
DE_INF("lcd cfg ok!\n");
if(LCD_IF_DSI == panel->lcd_if) {
#if defined(SUPPORT_DSI)
if(0 != dsi_cfg(screen_id, panel)) {
DE_WRN("dsi cfg fail!\n");
}
#endif
}
return 0;
}
