コード例 #1
0
ファイル: tomasulo.c プロジェクト: vonZuben/ece552
/* 
 * Description: 
 * 	Performs a cycle-by-cycle simulation of the 4-stage pipeline
 * Inputs:
 *      trace: instruction trace with all the instructions executed
 * Returns:
 * 	The total number of cycles it takes to execute the instructions.
 * Extra Notes:
 * 	sim_num_insn: the number of instructions in the trace
 */
counter_t runTomasulo(instruction_trace_t* trace)
{
    /* ECE552 Assignment 3 - BEGIN CODE */
    inst_queue.head = NULL;
    inst_queue.tail = NULL;
    /* ECE552 Assignment 3 - END CODE */
    
    //initialize instruction queue
    int i;
    for (i = 0; i < INSTR_QUEUE_SIZE; i++) {
      instr_queue[i] = NULL;
    }

    //initialize reservation stations
    for (i = 0; i < RESERV_INT_SIZE; i++) {
        reservINT[i] = NULL;
    }

    for(i = 0; i < RESERV_FP_SIZE; i++) {
        reservFP[i] = NULL;
    }

    //initialize functional units
    for (i = 0; i < FU_INT_SIZE; i++) {
      fuINT[i] = NULL;
    }

    for (i = 0; i < FU_FP_SIZE; i++) {
      fuFP[i] = NULL;
    }

    //initialize map_table to no producers
    int reg;
    for (reg = 0; reg < MD_TOTAL_REGS; reg++) {
      map_table[reg] = NULL;
    }
    
    int cycle = 1;
    while (true){

       /* ECE552: YOUR CODE GOES HERE */

        /* ECE552 Assignment 3 - BEGIN CODE */
        if (is_simulation_done(sim_num_insn))
            break;
        CDB_To_retire(cycle);
        execute_To_CDB(cycle);
        issue_To_execute(cycle); 
        dispatch_To_issue(cycle);
        fetch_To_dispatch(trace,cycle);
        cycle++;

        /* ECE552 Assignment 3 - END CODE */
    }
    
    return cycle;
}
コード例 #2
0
ファイル: tomasulo.c プロジェクト: sattarab/tomasulo
/* 
 * Description: 
 * 	Performs a cycle-by-cycle simulation of the 4-stage pipeline
 * Inputs:
 *      trace: instruction trace with all the instructions executed
 * Returns:
 * 	The total number of cycles it takes to execute the instructions.
 * Extra Notes:
 * 	sim_num_insn: the number of instructions in the trace
 */
counter_t runTomasulo(instruction_trace_t* trace) {
   //initialize instruction queue
   int i;
   for (i = 0; i < INSTR_QUEUE_SIZE; i++) {
      instr_queue[i] = NULL;
   }

	/* ECE552 Assignment 4 - BEGIN CODE */

	// removed the initialization for reservation stations as structured has changed.

  /* ECE552 Assignment 4 - END CODE */

		//initialize functional units
		for (i = 0; i < FU_INT_SIZE; i++) {
		  fuINT[i] = NULL;
		}

		for (i = 0; i < FU_FP_SIZE; i++) {
		  fuFP[i] = NULL;
		}

   //initialize map_table to no producers
   int reg;
   for (reg = 0; reg < MD_TOTAL_REGS; reg++) {
      map_table[reg] = NULL;
   }
  
   int cycle = 1;
   while (true) {

			/* ECE552 Assignment 4 - BEGIN CODE */
      
      CDB_To_retire(cycle);
      execute_To_CDB(cycle);
      issue_To_execute(cycle);
      dispatch_To_issue(cycle);
      fetch_To_dispatch(trace, cycle);

	
			if(fetch_index == trace->size - 1)
			{
				if(trace->next == NULL)
				{
					/* fetch has completed */
					fetch_completed = true;
				}
				else
				{
					/* reset the fetch index */
					fetch_index = 0;
					trace = trace->next;
				}
			}

      cycle++;
		/*if (cycle == 19400)
		{
			print_all_instr(trace, 20000);
			/*print_list(reservFP, "reservFP", 2);

			int i;
			for (i = 0; i < INSTR_QUEUE_SIZE; i++)
			{
				if (instr_queue[i] != NULL)
				{
					print_insn(instr_queue[i], "instr_queue");
				}
			}
			if (commonDataBus != NULL)
			print_insn(commonDataBus, "commonDataBus");*/
		//}
			//print_all_instr(trace, 100000);

      if (is_simulation_done(trace, sim_num_insn))
			{
				break;
			}

		/* ECE552 Assignment 4 - END CODE */
   }
  
   return cycle;
}