/** * \brief configure DMA transfer descriptor. */ static void setup_transfer_descriptor(DmacDescriptor *descriptor) { struct dma_descriptor_config descriptor_config; if (true == is_scrolling) { /* Get the default configuration */ dma_descriptor_get_config_defaults(&descriptor_config); descriptor_config.beat_size = DMA_BEAT_SIZE_WORD; descriptor_config.src_increment_enable = true; descriptor_config.dst_increment_enable = false; descriptor_config.step_size = (DMA_ADDRESS_INCREMENT_STEP_SIZE_1); descriptor_config.step_selection = DMA_STEPSEL_SRC; descriptor_config.block_action = DMA_BLOCK_ACTION_INT; /* DMA transfer count found by Block count variable at * run time from the scrolling string. */ descriptor_config.block_transfer_count = dma_block_count; descriptor_config.source_address = (uint32_t)dma_source_buf + (dma_block_count * sizeof(dma_source_buf[0])); descriptor_config.destination_address = (uint32_t)(&SLCD->CMDATA.reg); descriptor_config.next_descriptor_address = ( uint32_t )descriptor; /* Create a DMA descriptor */ dma_descriptor_create(descriptor, &descriptor_config); } if (true == is_bitmapping) { /* Get the default configuration */ dma_descriptor_get_config_defaults(&descriptor_config); descriptor_config.beat_size = DMA_BEAT_SIZE_WORD; descriptor_config.src_increment_enable = true; descriptor_config.dst_increment_enable = false; descriptor_config.step_size = (DMA_ADDRESS_INCREMENT_STEP_SIZE_1); descriptor_config.step_selection = DMA_STEPSEL_SRC; descriptor_config.block_action = DMA_BLOCK_ACTION_INT; /* Block count manipulated number of the frame elements respective * style chosen by the user at run time. */ descriptor_config.block_transfer_count = dma_block_count; descriptor_config.source_address = (uint32_t)dma_source_buf + (dma_block_count * sizeof(dma_source_buf[0])); descriptor_config.destination_address = (uint32_t)(&SLCD->ISDATA.reg); descriptor_config.next_descriptor_address = (uint32_t)descriptor; /* Create a DMA descriptor */ dma_descriptor_create(descriptor, &descriptor_config); } }
/** * \brief Configure DMA AES DATA read trigger. */ static void configure_dma_aes_rd(void) { struct dma_resource_config rx_config; dma_get_config_defaults(&rx_config); rx_config.peripheral_trigger = AES_DMAC_ID_RD; rx_config.trigger_action = DMA_TRIGGER_ACTON_BLOCK; /* Allocate DMA resource.*/ dma_allocate(&example_resource_rx, &rx_config); struct dma_descriptor_config rx_descriptor_config; dma_descriptor_get_config_defaults(&rx_descriptor_config); rx_descriptor_config.beat_size = DMA_BEAT_SIZE_WORD; rx_descriptor_config.src_increment_enable = false; rx_descriptor_config.block_transfer_count = AES_EXAMPLE_REFBUF_SIZE; rx_descriptor_config.source_address = (uint32_t)&(AES->INDATA); rx_descriptor_config.destination_address = (uint32_t)output_data + sizeof(output_data); /* Create a DMA transfer descriptor.*/ dma_descriptor_create(&example_descriptor_rx, &rx_descriptor_config); /* Add DMA transfer descriptor to DMA resource.*/ dma_add_descriptor(&example_resource_rx, &example_descriptor_rx); }
//! [config_dma_for_wave] static void config_dma_for_wave(void) { //! [config_dma_resource_for_wave] struct dma_resource_config config; dma_get_config_defaults(&config); config.trigger_action = DMA_TRIGGER_ACTON_BEAT; config.peripheral_trigger = CONF_COMPARE_TRIGGER; dma_allocate(&compare_dma_resource, &config); //! [config_dma_resource_for_wave] //! [config_dma_descriptor_for_wave] struct dma_descriptor_config descriptor_config; dma_descriptor_get_config_defaults(&descriptor_config); descriptor_config.block_transfer_count = 3; descriptor_config.beat_size = DMA_BEAT_SIZE_HWORD; descriptor_config.dst_increment_enable = false; descriptor_config.source_address = (uint32_t)compare_values + sizeof(compare_values); descriptor_config.destination_address = (uint32_t)&CONF_PWM_MODULE->CC[CONF_PWM_CHANNEL]; dma_descriptor_create(&compare_dma_descriptor, &descriptor_config); //! [config_dma_descriptor_for_wave] //! [config_dma_job_for_wave] dma_add_descriptor(&compare_dma_resource, &compare_dma_descriptor); dma_add_descriptor(&compare_dma_resource, &compare_dma_descriptor); dma_start_transfer_job(&compare_dma_resource); //! [config_dma_job_for_wave] }
/** * \brief Configure DMA AES DATA write trigger. */ static void configure_dma_aes_wr(void) { struct dma_resource_config tx_config; dma_get_config_defaults(&tx_config); tx_config.peripheral_trigger = AES_DMAC_ID_WR; tx_config.trigger_action = DMA_TRIGGER_ACTON_BLOCK; /* Allocate DMA resource.*/ dma_allocate(&example_resource_tx, &tx_config); struct dma_descriptor_config tx_descriptor_config; dma_descriptor_get_config_defaults(&tx_descriptor_config); tx_descriptor_config.beat_size = DMA_BEAT_SIZE_WORD; tx_descriptor_config.dst_increment_enable = false; tx_descriptor_config.block_transfer_count = AES_EXAMPLE_REFBUF_SIZE; tx_descriptor_config.source_address = (uint32_t)ref_plain_text + sizeof(ref_plain_text); tx_descriptor_config.destination_address =(uint32_t) &(AES->INDATA); dma_descriptor_create(&example_descriptor_tx, &tx_descriptor_config); /* Add DMA transfer descriptor to DMA resource.*/ dma_add_descriptor(&example_resource_tx, &example_descriptor_tx); }
//! [config_dma_for_tx] static void _config_dma_for_tx(void) { //! [config_dma_resource_for_tx] struct dma_resource_config config; dma_get_config_defaults(&config); config.trigger_action = DMA_TRIGGER_ACTON_BEAT; config.peripheral_trigger = CONF_TX_TRIGGER; dma_allocate(&tx_dma_resource, &config); //! [config_dma_resource_for_tx] //! [config_dma_descriptor_for_tx] struct dma_descriptor_config descriptor_config; dma_descriptor_get_config_defaults(&descriptor_config); descriptor_config.block_transfer_count = 4; descriptor_config.beat_size = DMA_BEAT_SIZE_HWORD; descriptor_config.dst_increment_enable = false; descriptor_config.source_address = (uint32_t)tx_values + sizeof(tx_values); descriptor_config.destination_address = (uint32_t)&CONF_I2S_MODULE->DATA[0]; dma_descriptor_create(&tx_dma_descriptor, &descriptor_config); tx_dma_descriptor.DESCADDR.reg = (uint32_t)&tx_dma_descriptor; //! [config_dma_descriptor_for_tx] //! [config_dma_job_for_tx] dma_add_descriptor(&tx_dma_resource, &tx_dma_descriptor); dma_start_transfer_job(&tx_dma_resource); //! [config_dma_job_for_tx] }
//! [config_dma_for_rx] static void _config_dma_for_rx(void) { //! [config_dma_resource_for_rx] //! [dma_setup_1] struct dma_resource_config config; //! [dma_setup_1] //! [dma_setup_2] dma_get_config_defaults(&config); //! [dma_setup_2] //! [dma_setup_3] config.trigger_action = DMA_TRIGGER_ACTON_BEAT; config.peripheral_trigger = CONF_RX_TRIGGER; //! [dma_setup_3] //! [dma_setup_4] dma_allocate(&rx_dma_resource, &config); //! [dma_setup_4] //! [config_dma_resource_for_rx] //! [config_dma_descriptor_for_rx] //! [dma_setup_5] struct dma_descriptor_config descriptor_config; //! [dma_setup_5] //! [dma_setup_6] dma_descriptor_get_config_defaults(&descriptor_config); //! [dma_setup_6] //! [dma_setup_7] descriptor_config.block_transfer_count = 4; descriptor_config.beat_size = DMA_BEAT_SIZE_HWORD; descriptor_config.step_selection = DMA_STEPSEL_SRC; descriptor_config.src_increment_enable = false; descriptor_config.destination_address = (uint32_t)rx_values + sizeof(rx_values); descriptor_config.source_address = (uint32_t)&CONF_I2S_MODULE->DATA[1]; //! [dma_setup_7] //! [dma_setup_8] dma_descriptor_create(&rx_dma_descriptor, &descriptor_config); //! [dma_setup_8] //! [dma_setup_9] rx_dma_descriptor.DESCADDR.reg = (uint32_t)&rx_dma_descriptor; //! [dma_setup_9] //! [config_dma_descriptor_for_rx] //! [config_dma_job_for_rx] //! [dma_setup_10] dma_add_descriptor(&rx_dma_resource, &rx_dma_descriptor); //! [dma_setup_10] //! [dma_setup_11] dma_start_transfer_job(&rx_dma_resource); //! [dma_setup_11] //! [config_dma_job_for_rx] }
//! [config_dma_for_capture] static void config_dma_for_capture(void) { //! [config_dma_resource_for_capture] //! [dma_setup_1] struct dma_resource_config config; //! [dma_setup_1] //! [dma_setup_2] dma_get_config_defaults(&config); //! [dma_setup_2] //! [dma_setup_3] config.trigger_action = DMA_TRIGGER_ACTON_BEAT; config.peripheral_trigger = CONF_CAPTURE_TRIGGER; //! [dma_setup_3] //! [dma_setup_4] dma_allocate(&capture_dma_resource, &config); //! [dma_setup_4] //! [config_dma_resource_for_capture] //! [config_dma_descriptor_for_capture] //! [dma_setup_5] struct dma_descriptor_config descriptor_config; //! [dma_setup_5] //! [dma_setup_6] dma_descriptor_get_config_defaults(&descriptor_config); //! [dma_setup_6] //! [dma_setup_7] descriptor_config.block_transfer_count = 3; descriptor_config.beat_size = DMA_BEAT_SIZE_HWORD; descriptor_config.step_selection = DMA_STEPSEL_SRC; descriptor_config.src_increment_enable = false; descriptor_config.source_address = (uint32_t)&CONF_PWM_MODULE->CC[CONF_TCC_CAPTURE_CHANNEL]; descriptor_config.destination_address = (uint32_t)capture_values + sizeof(capture_values); //! [dma_setup_7] //! [dma_setup_8] dma_descriptor_create(&capture_dma_descriptor, &descriptor_config); //! [dma_setup_8] //! [config_dma_descriptor_for_capture] //! [config_dma_job_for_capture] //! [dma_setup_10] dma_add_descriptor(&capture_dma_resource, &capture_dma_descriptor); dma_add_descriptor(&capture_dma_resource, &capture_dma_descriptor); //! [dma_setup_10] //! [dma_setup_11] dma_start_transfer_job(&capture_dma_resource); //! [dma_setup_11] //! [config_dma_job_for_capture] }
static void setup_transfer_descriptor_tx(DmacDescriptor *tx_descriptor) { struct dma_descriptor_config tx_descriptor_config; dma_descriptor_get_config_defaults(&tx_descriptor_config); tx_descriptor_config.beat_size = DMA_BEAT_SIZE_BYTE; tx_descriptor_config.dst_increment_enable = false; tx_descriptor_config.block_transfer_count = sizeof(buffer_tx)/sizeof(uint8_t); tx_descriptor_config.source_address = (uint32_t)buffer_tx + sizeof(buffer_tx); tx_descriptor_config.destination_address = (uint32_t)(&spi_master_instance_ADXL.hw->SPI.DATA.reg); dma_descriptor_create(tx_descriptor, &tx_descriptor_config); }
static void setup_transfer_descriptor_rx(DmacDescriptor *rx_descriptor) { struct dma_descriptor_config rx_descriptor_config; dma_descriptor_get_config_defaults(&rx_descriptor_config); rx_descriptor_config.beat_size = DMA_BEAT_SIZE_HWORD; rx_descriptor_config.src_increment_enable = false; rx_descriptor_config.block_transfer_count = 64; ///rx_descriptor_config.block_transfer_count = sizeof(buffer_rx)/sizeof(buffer_rx); rx_descriptor_config.source_address = (uint32_t)(ADXL345_DATAX0 | ADXL345_SPI_READ); //rx_descriptor_config.source_address = (uint32_t)(&spi_master_instance_ADXL.hw->SPI.DATA.reg); rx_descriptor_config.destination_address = (uint32_t)buffer_x; //rx_descriptor_config.destination_address = (uint32_t)buffer_rx + sizeof(buffer_rx); dma_descriptor_create(rx_descriptor, &rx_descriptor_config); }
/** * \brief Configure DMA channel descriptor * \param descriptor DMA channel descriptor * \param descriptor_num Descriptor to be configured */ void setup_transfer_descriptor(DmacDescriptor *descriptor, uint8_t descriptor_num) { /* DMA descriptor configuration setup */ struct dma_descriptor_config descriptor_config; /* Get default configuration */ dma_descriptor_get_config_defaults(&descriptor_config); /* Set beat size as byte */ descriptor_config.beat_size = DMA_BEAT_SIZE_BYTE; /* Set block count as 1024 beats */ descriptor_config.block_transfer_count = BLOCK_COUNT; /* Trigger interrupt once block transfer is complete */ descriptor_config.block_action = DMA_BLOCK_ACTION_INT; switch (descriptor_num){ case DMAC_DESCRIPTOR1_ID: /* Source address is static as it is ADC result register */ descriptor_config.src_increment_enable = false; /* * Enable event for every beat transfer (I.e. byte in this case) * Every byte transfer occurs for each sample from ADC. * I.e. Event is triggered for every ADC result ready. */ descriptor_config.event_output_selection = DMA_EVENT_OUTPUT_BEAT; /* Destination address is static as it is USART DATA register */ descriptor_config.dst_increment_enable = false; /* Set source address as ADC RESULT register */ descriptor_config.source_address = (uint32_t)(&ADC->RESULT.reg); /* Set destination address as USART DATA register */ descriptor_config.destination_address = (uint32_t)(&SERCOM2->USART.DATA.reg); break; default: Assert(false); break; } /* Create descriptor */ dma_descriptor_create(descriptor, &descriptor_config); }
//! [setup_dma_transfer_descriptor] static void setup_transfer_descriptor(DmacDescriptor *descriptor ) { //! [setup_4] struct dma_descriptor_config descriptor_config; //! [setup_4] //! [setup_5] dma_descriptor_get_config_defaults(&descriptor_config); //! [setup_5] //! [setup_6] descriptor_config.block_transfer_count = sizeof(source_memory); descriptor_config.source_address = (uint32_t)source_memory + sizeof(source_memory); descriptor_config.destination_address = (uint32_t)destination_memory + sizeof(source_memory); //! [setup_6] //! [setup_7] dma_descriptor_create(descriptor, &descriptor_config); //! [setup_7] }