void AJ_WSL_SPI_DMATransfer(void* buffer, uint32_t size, uint8_t direction)
{
dma_transfer_descriptor_t transfer;
AJ_ASSERT(AJ_WSL_DMA_send_done == 0);
/* Disable both channels before parameters are set */
dmac_channel_disable(DMAC, AJ_DMA_TX_CHANNEL);
dmac_channel_disable(DMAC, AJ_DMA_RX_CHANNEL);
if (direction == AJ_DMA_TX) {
/* Direction is TX so set the destination to the SPI hardware */
transfer = transfer_descriptors[AJ_DMA_TX][AJ_DMA_TX_CHANNEL];
/* Set the source to the buffer your sending */
transfer.ul_source_addr = (uint32_t) buffer;
transfer.ul_ctrlA |= size;
dmac_channel_single_buf_transfer_init(DMAC, AJ_DMA_TX_CHANNEL, (dma_transfer_descriptor_t*) &transfer);
/* Enable the channel to start DMA */
dmac_channel_enable(DMAC, AJ_DMA_TX_CHANNEL);
/* Setup RX direction as NULL destination and SPI0 as source */
transfer = transfer_descriptors[AJ_DMA_TX][AJ_DMA_RX_CHANNEL];
transfer.ul_ctrlA |= size;
dmac_channel_single_buf_transfer_init(DMAC, AJ_DMA_RX_CHANNEL, &transfer);
/* Enable the channel to start DMA */
dmac_channel_enable(DMAC, AJ_DMA_RX_CHANNEL);
/* Wait for the transfer to complete */
while (!AJ_WSL_DMA_send_done);
} else {
/* We are transferring in the RX direction */
/* Set up the destination address */
transfer = transfer_descriptors[AJ_DMA_RX][AJ_DMA_RX_CHANNEL];
transfer.ul_destination_addr = (uint32_t) buffer;
transfer.ul_ctrlA |= size;
dmac_channel_single_buf_transfer_init(DMAC, AJ_DMA_RX_CHANNEL, &transfer);
dmac_channel_enable(DMAC, AJ_DMA_RX_CHANNEL);
/* Setup the TX channel to transfer from a NULL pointer
* This must be done in order for the transfer to start
*/
transfer = transfer_descriptors[AJ_DMA_RX][AJ_DMA_TX_CHANNEL];
transfer.ul_ctrlA |= size;
dmac_channel_single_buf_transfer_init(DMAC, AJ_DMA_TX_CHANNEL, (dma_transfer_descriptor_t*) &transfer);
dmac_channel_enable(DMAC, AJ_DMA_TX_CHANNEL);
while (!AJ_WSL_DMA_send_done);
}
/* reset the DMA completed indicator */
AJ_WSL_DMA_send_done = 0;
dmac_channel_disable(DMAC, AJ_DMA_TX_CHANNEL);
dmac_channel_disable(DMAC, AJ_DMA_RX_CHANNEL);
}
void channel4_trans_start(u32 srcadr, u32 dstadr, u16 trans_blk)
{
DMA_SAR4L = srcadr;
DMA_DAR4L = dstadr;
DMA_CTL4H = trans_blk;
dmac_channel_enable(4);
}
/**
* \brief DMAC tx channel configuration.
*/
static void configure_dmac_tx(void)
{
uint32_t ul_cfg;
dma_transfer_descriptor_t dmac_trans;
ul_cfg = 0;
ul_cfg |= DMAC_CFG_DST_PER(USART_TX_IDX) |
DMAC_CFG_DST_H2SEL |
DMAC_CFG_SOD_ENABLE | DMAC_CFG_FIFOCFG_ALAP_CFG;
dmac_channel_set_configuration(DMAC, BOARD_USART_DMAC_TX_CH, ul_cfg);
dmac_channel_disable(DMAC, BOARD_USART_DMAC_TX_CH);
dmac_trans.ul_source_addr = (uint32_t) gs_puc_buffer;
dmac_trans.ul_destination_addr = (uint32_t) & BOARD_USART->US_THR;
dmac_trans.ul_ctrlA =
DMAC_CTRLA_BTSIZE(BUFFER_SIZE) |
DMAC_CTRLA_SRC_WIDTH_BYTE | DMAC_CTRLA_DST_WIDTH_BYTE;
dmac_trans.ul_ctrlB =
DMAC_CTRLB_SRC_DSCR | DMAC_CTRLB_DST_DSCR |
DMAC_CTRLB_FC_MEM2PER_DMA_FC |
DMAC_CTRLB_SRC_INCR_INCREMENTING |
DMAC_CTRLB_DST_INCR_FIXED;
dmac_trans.ul_descriptor_addr = 0;
dmac_channel_single_buf_transfer_init(DMAC, BOARD_USART_DMAC_TX_CH,
&dmac_trans);
dmac_channel_enable(DMAC, BOARD_USART_DMAC_TX_CH);
}
/**
* \brief Start DMA sending data.
*
* \param p_buffer Pointer to the data to be transmitted.
* \param us_size Size of the data to be transmitted.
*/
static void ssc_dma(void *p_buffer, uint16_t us_size)
{
dma_transfer_descriptor_t desc;
desc.ul_source_addr = (uint32_t)p_buffer;
desc.ul_destination_addr = (uint32_t)(&SSC->SSC_THR);
desc.ul_ctrlA = DMAC_CTRLA_BTSIZE(us_size)
| DMAC_CTRLA_SRC_WIDTH_HALF_WORD
| DMAC_CTRLA_DST_WIDTH_HALF_WORD;
desc.ul_ctrlB = DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE
| DMAC_CTRLB_DST_DSCR_FETCH_DISABLE
| DMAC_CTRLB_FC_MEM2PER_DMA_FC
| DMAC_CTRLB_SRC_INCR_INCREMENTING
| DMAC_CTRLB_DST_INCR_FIXED
| DMAC_CTRLB_IEN;
desc.ul_descriptor_addr = NULL;
dmac_channel_single_buf_transfer_init(DMAC, DMA_CH, &desc);
/* Start DMA transfer */
dmac_channel_enable(DMAC, DMA_CH);
/* Enable SSC transmitter */
ssc_enable_tx(SSC);
}
void channel5_llp_enable(u8 src_hs_ch, u8 dst_hs_ch, u32 llp_cur_adr){
REG32(DMA_CFG5H) = (src_hs_ch<<7) | (dst_hs_ch<<11);
REG32(DMA_CFG5L) = 0;
//DMA_CTL4L = (1<<25) | (0<<23); //SRC SEL M2,DST SEL M1
REG32(DMA_CTL5L) = (1<<28) | (1<<27);
REG32(DMA_LLP5L) = llp_cur_adr & 0xfffffffC;
dmac_channel_enable(5);
}
void channel4_llp_enable(u8 src_hs_ch, u8 dst_hs_ch, u32 llp_cur_adr){
DMA_CFG4H = (src_hs_ch<<7) | (dst_hs_ch<<11); //SET CHannel 4 handshake channel num
DMA_CFG4L = 0;
DMA_CTL4L = (0<<25) | (1<<23); //SRC SEL M1,DST SEL M2
DMA_CTL4L = (1<<28) | (1<<27); //SRC LLP ENABLE,and DST LLP ENABLE
//DMA_LLP4L = llp_cur_adr & 0xfffffff3;
DMA_LLP4L = llp_cur_adr & 0xfffffffC;
dmac_channel_enable(4);
}
//------------------------------------------------------------------------------
// start RX DMA
static void spiDmaRX(uint8_t* dst, uint16_t count) {
dmac_channel_disable(SPI_DMAC_RX_CH);
DMAC->DMAC_CH_NUM[SPI_DMAC_RX_CH].DMAC_SADDR = (uint32_t)&SPI0->SPI_RDR;
DMAC->DMAC_CH_NUM[SPI_DMAC_RX_CH].DMAC_DADDR = (uint32_t)dst;
DMAC->DMAC_CH_NUM[SPI_DMAC_RX_CH].DMAC_DSCR = 0;
DMAC->DMAC_CH_NUM[SPI_DMAC_RX_CH].DMAC_CTRLA = count |
DMAC_CTRLA_SRC_WIDTH_BYTE | DMAC_CTRLA_DST_WIDTH_BYTE;
DMAC->DMAC_CH_NUM[SPI_DMAC_RX_CH].DMAC_CTRLB = DMAC_CTRLB_SRC_DSCR |
DMAC_CTRLB_DST_DSCR | DMAC_CTRLB_FC_PER2MEM_DMA_FC |
DMAC_CTRLB_SRC_INCR_FIXED | DMAC_CTRLB_DST_INCR_INCREMENTING;
DMAC->DMAC_CH_NUM[SPI_DMAC_RX_CH].DMAC_CFG = DMAC_CFG_SRC_PER(SPI_RX_IDX) |
DMAC_CFG_SRC_H2SEL | DMAC_CFG_SOD | DMAC_CFG_FIFOCFG_ASAP_CFG;
dmac_channel_enable(SPI_DMAC_RX_CH);
}
/**
* \brief Test DMA single buffer transfer with polling mode.
*
* \param test Current test case.
*/
static void run_single_buf_xfer_test(const struct test_case *test)
{
uint32_t i;
uint32_t cfg;
dma_transfer_descriptor_t desc;
/* Initialize DMA buffer */
for (i = 0; i < DMA_BUF_SIZE; i++) {
g_dma_buf[0][i] = i;
g_dma_buf[1][i] = 0;
}
/* Initialize and enable DMA controller */
pmc_enable_periph_clk(ID_DMAC);
dmac_init(DMAC);
dmac_set_priority_mode(DMAC, DMAC_PRIORITY_ROUND_ROBIN);
dmac_enable(DMAC);
/* Set for channel configuration register */
cfg = DMAC_CFG_SOD_ENABLE | /* Enable stop on done */
DMAC_CFG_AHB_PROT(1) | /* Set AHB Protection */
DMAC_CFG_FIFOCFG_ALAP_CFG; /* FIFO Configuration */
dmac_channel_set_configuration(DMAC, DMA_CH, cfg);
/* Initialize single buffer transfer: buffer 0 -> buffer 1 */
desc.ul_source_addr = (uint32_t) g_dma_buf[0];
desc.ul_destination_addr = (uint32_t) g_dma_buf[1];
desc.ul_ctrlA = DMAC_CTRLA_BTSIZE(DMA_BUF_SIZE) | /* Set Buffer Transfer Size */
DMAC_CTRLA_SRC_WIDTH_WORD | /* Source transfer size is set to 32-bit width */
DMAC_CTRLA_DST_WIDTH_WORD; /* Destination transfer size is set to 32-bit width */
desc.ul_ctrlB = DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE | /* Buffer Descriptor Fetch operation is disabled for the source */
DMAC_CTRLB_DST_DSCR_FETCH_DISABLE | /* Buffer Descriptor Fetch operation is disabled for the destination */
DMAC_CTRLB_FC_MEM2MEM_DMA_FC | /* Memory-to-Memory Transfer */
DMAC_CTRLB_SRC_INCR_INCREMENTING | /* The source address is incremented */
DMAC_CTRLB_DST_INCR_INCREMENTING; /* The destination address is incremented */
desc.ul_descriptor_addr = 0; /* No descriptor for single transfer */
dmac_channel_single_buf_transfer_init(DMAC, DMA_CH, &desc);
/* Start DMA transfer and wait for finish */
dmac_channel_enable(DMAC, DMA_CH);
while (!dmac_channel_is_transfer_done(DMAC, DMA_CH)) {
}
/* Verify the transferred data */
for (i = 0; i < DMA_BUF_SIZE; i++) {
test_assert_true(test, g_dma_buf[0][i] == g_dma_buf[1][i],
"Data comparison failed.");
}
}
void spi_start_transmit_dma(Dmac *p_dmac, Spi *p_spi, uint32_t ul_num,
const void *src, uint32_t nb_bytes)
{
static uint8_t ff = 0xFF;
uint32_t cfg, src_incr = DMAC_CTRLB_SRC_INCR_INCREMENTING;
dma_transfer_descriptor_t desc;
// Send 0xFF repeatedly if src is NULL
if (!src) {
src = &ff;
src_incr = DMAC_CTRLB_SRC_INCR_FIXED;
}
// Disable the DMA channel prior to configuring
dmac_enable(p_dmac);
dmac_channel_disable(p_dmac, ul_num);
cfg = DMAC_CFG_SOD
| DMAC_CFG_DST_H2SEL
| DMAC_CFG_DST_PER(SPI_TX_IDX)
| DMAC_CFG_FIFOCFG_ALAP_CFG;
dmac_channel_set_configuration(p_dmac, ul_num, cfg);
// Prepare DMA transfer
desc.ul_source_addr = (uint32_t)src;
desc.ul_destination_addr = (uint32_t)&(p_spi->SPI_TDR);
desc.ul_ctrlA = DMAC_CTRLA_BTSIZE(nb_bytes)
| DMAC_CTRLA_SRC_WIDTH_BYTE
| DMAC_CTRLA_DST_WIDTH_BYTE;
desc.ul_ctrlB = DMAC_CTRLB_SRC_DSCR
| DMAC_CTRLB_DST_DSCR
| DMAC_CTRLB_FC_MEM2PER_DMA_FC
| src_incr
| DMAC_CTRLB_DST_INCR_FIXED;
// Next field is ignored, but set it anyway
desc.ul_descriptor_addr = (uint32_t)NULL;
// Finish configuring the transfer
dmac_channel_single_buf_transfer_init(p_dmac, ul_num, &desc);
// And now start the DMA transfer
dmac_channel_enable(p_dmac, ul_num);
}
void spi_start_receive_dma(Dmac *p_dmac, Spi *p_spi, uint32_t ul_num,
const void *dest, uint32_t nb_bytes)
{
uint32_t cfg;
dma_transfer_descriptor_t desc;
// clear any potential overrun error
cfg = p_spi->SPI_SR;
// Turn the DMA channel off before configuring
dmac_enable(p_dmac);
dmac_channel_disable(p_dmac, ul_num);
cfg = DMAC_CFG_SOD
| DMAC_CFG_SRC_H2SEL
| DMAC_CFG_SRC_PER(SPI_RX_IDX)
| DMAC_CFG_FIFOCFG_ASAP_CFG;
dmac_channel_set_configuration(p_dmac, ul_num, cfg);
// Prepare DMA transfer
desc.ul_source_addr = (uint32_t)&(p_spi->SPI_RDR);
desc.ul_destination_addr = (uint32_t)dest;
desc.ul_ctrlA = DMAC_CTRLA_BTSIZE(nb_bytes)
| DMAC_CTRLA_SRC_WIDTH_BYTE
| DMAC_CTRLA_DST_WIDTH_BYTE;
desc.ul_ctrlB = DMAC_CTRLB_SRC_DSCR
| DMAC_CTRLB_DST_DSCR
| DMAC_CTRLB_FC_PER2MEM_DMA_FC
| DMAC_CTRLB_SRC_INCR_FIXED
| DMAC_CTRLB_DST_INCR_INCREMENTING;
// This next field is ignored but set it anyway
desc.ul_descriptor_addr = (uint32_t)NULL;
// Finish configuring the DMA transfer
dmac_channel_single_buf_transfer_init(p_dmac, ul_num, &desc);
// And now allow the DMA transfer to begin
dmac_channel_enable(p_dmac, ul_num);
}
//------------------------------------------------------------------------------
// start TX DMA
static void spiDmaTX(const uint8_t* src, uint16_t count) {
static uint8_t ff = 0XFF;
uint32_t src_incr = DMAC_CTRLB_SRC_INCR_INCREMENTING;
if (!src) {
src = &ff;
src_incr = DMAC_CTRLB_SRC_INCR_FIXED;
}
dmac_channel_disable(SPI_DMAC_TX_CH);
DMAC->DMAC_CH_NUM[SPI_DMAC_TX_CH].DMAC_SADDR = (uint32_t)src;
DMAC->DMAC_CH_NUM[SPI_DMAC_TX_CH].DMAC_DADDR = (uint32_t)&SPI0->SPI_TDR;
DMAC->DMAC_CH_NUM[SPI_DMAC_TX_CH].DMAC_DSCR = 0;
DMAC->DMAC_CH_NUM[SPI_DMAC_TX_CH].DMAC_CTRLA = count |
DMAC_CTRLA_SRC_WIDTH_BYTE | DMAC_CTRLA_DST_WIDTH_BYTE;
DMAC->DMAC_CH_NUM[SPI_DMAC_TX_CH].DMAC_CTRLB = DMAC_CTRLB_SRC_DSCR |
DMAC_CTRLB_DST_DSCR | DMAC_CTRLB_FC_MEM2PER_DMA_FC |
src_incr | DMAC_CTRLB_DST_INCR_FIXED;
DMAC->DMAC_CH_NUM[SPI_DMAC_TX_CH].DMAC_CFG = DMAC_CFG_DST_PER(SPI_TX_IDX) |
DMAC_CFG_DST_H2SEL | DMAC_CFG_SOD | DMAC_CFG_FIFOCFG_ALAP_CFG;
dmac_channel_enable(SPI_DMAC_TX_CH);
}
void audio_AGC_DMA_Isr(void)
{
u32 agc_sta = rd_reg(AGC_STA);
//deg_Printf(" %x\n",agc_sta);
if((agc_sta & 0x1) == 0x1)
wr_reg(AGC_CFG_CLR, rd_reg(AGC_CFG_CLR)|BIT(0));
wr_reg(AGC_CFG0,rd_reg(AGC_CFG0)&(~BIT(5)));
if((g_stcJpegInfo.iAudioFillBufCnt+1) < (g_stcJpegInfo.iAudioFSWriteBufCnt + AUDIO_BUFFER_NUM))
{
if(audio_buffer_ptr == ((u32)JPEG_BUFFER_END_ADDRESS - 0x2000))
audio_buffer_ptr = (u32)JPEG_BUFFER_END_ADDRESS-(AUDIO_BUFFER_NUM*0x2000);
else
audio_buffer_ptr += g_stcJpegInfo.dwAudiobufSize;
g_stcJpegInfo.iAudioFillBufCnt++;
}
else
{
deg_Printf("d");
g_stcJpegInfo.i30FrameCnt -=((192*(u32Framecount+1))/25 -(192*u32Framecount)/25);
u32Framecount++;
if(u32Framecount >= 25)
{
u32Framecount = 0;
}
g_stcJpegInfo.iJpeg10MSCnt -= 25;
}
dmac_channel_disable(AUDIO_ADC_DMA_CH);
//dma_peri2mem_Ext(AUDIO_ADC_DMA_CH, (0<<11)|(6<<7)|(0<<1), (0<<11)|(0<<10), AUADC_DMA_TX_ADR, (audio_buffer_ptr+8), (2048-2));
REG32(DMA_DAR0L + AUDIO_ADC_DMA_CH*0x58) = (u32)(audio_buffer_ptr+8);
dmac_channel_enable(AUDIO_ADC_DMA_CH);
wr_reg(AGC_CFG0,rd_reg(AGC_CFG0)|(BIT(5)));
wr_reg(AGC_CFG_CLR, rd_reg(AGC_CFG_CLR)|BIT(5));
}
void channel3_trans_start(u32 srcadr, u32 dstadr, u16 trans_blk){
DMA_SAR3L = srcadr;
DMA_DAR3L = dstadr;
DMA_CTL3H = trans_blk;
dmac_channel_enable(3);
}
void channel2_trans_start(u32 srcadr, u32 dstadr, u16 trans_blk){
DMA_SAR2L = srcadr;
DMA_DAR2L = dstadr;
DMA_CTL2H = trans_blk;
dmac_channel_enable(2);
}
/**
* \brief Test DMA multiple buffer transfer with interrupt mode.
*/
static void test_multi_buf_xfer(void)
{
uint32_t i;
uint32_t cfg;
dma_transfer_descriptor_t desc[3];
printf("\n\rTest multiple buffer transfer...\n\r");
/* Initialize DMA buffer */
for (i = 0; i < DMA_BUF_SIZE; i++) {
g_dma_buf[0][i] = i;
g_dma_buf[1][i] = i + 10;
g_dma_buf[2][i] = i + 20;
g_dma_buf[3][i] = 0;
g_dma_buf[4][i] = 0;
g_dma_buf[5][i] = 0;
}
/* Initialize and enable DMA controller */
pmc_enable_periph_clk(ID_DMAC);
dmac_init(DMAC);
dmac_set_priority_mode(DMAC, DMAC_PRIORITY_ROUND_ROBIN);
dmac_enable(DMAC);
/* Set for channel configuration register */
cfg = DMAC_CFG_SOD_DISABLE | /* Disable stop on done */
DMAC_CFG_AHB_PROT(1) | /* Set AHB Protection */
DMAC_CFG_FIFOCFG_ALAP_CFG; /* FIFO Configuration */
dmac_channel_set_configuration(DMAC, 0, cfg);
/* Initialize multiple buffer transfer (LLI) :
* buffer 0 -> buffer 3
* buffer 1 -> buffer 4
* buffer 2 -> buffer 5
*/
desc[0].ul_source_addr = (uint32_t) g_dma_buf[0];
desc[0].ul_destination_addr = (uint32_t) g_dma_buf[3];
/*
* Set DMA CTRLA:
* - Set Buffer Transfer Size
* - Source transfer size is set to 32-bit width
* - Destination transfer size is set to 32-bit width
*/
desc[0].ul_ctrlA = DMAC_CTRLA_BTSIZE(DMA_BUF_SIZE) |
DMAC_CTRLA_SRC_WIDTH_WORD |
DMAC_CTRLA_DST_WIDTH_WORD;
/*
* Set DMA CTRLB:
* - Descriptor is fetched from the memory
* - Descriptor is fetched from the memory
* - Memory-to-Memory Transfer
* - The source address is incremented
* - The destination address is incremented
*/
desc[0].ul_ctrlB = DMAC_CTRLB_SRC_DSCR_FETCH_FROM_MEM |
DMAC_CTRLB_DST_DSCR_FETCH_FROM_MEM |
DMAC_CTRLB_FC_MEM2MEM_DMA_FC |
DMAC_CTRLB_SRC_INCR_INCREMENTING |
DMAC_CTRLB_DST_INCR_INCREMENTING;
/* Pointer to next descriptor */
desc[0].ul_descriptor_addr = (uint32_t) &desc[1];
desc[1].ul_source_addr = (uint32_t) g_dma_buf[1];
desc[1].ul_destination_addr = (uint32_t) g_dma_buf[4];
/*
* Set DMA CTRLA:
* - Set Buffer Transfer Size
* - Source transfer size is set to 32-bit width
* - Destination transfer size is set to 32-bit width
*/
desc[1].ul_ctrlA = DMAC_CTRLA_BTSIZE(DMA_BUF_SIZE) |
DMAC_CTRLA_SRC_WIDTH_WORD |
DMAC_CTRLA_DST_WIDTH_WORD;
/*
* Set DMA CTRLB:
* - Source descriptor is fetched from the memory
* - Destination descriptor is fetched from the memory
* - Memory-to-Memory Transfer
* - The source address is incremented
* - The destination address is incremented
*/
desc[1].ul_ctrlB = DMAC_CTRLB_SRC_DSCR_FETCH_FROM_MEM |
DMAC_CTRLB_DST_DSCR_FETCH_FROM_MEM |
DMAC_CTRLB_FC_MEM2MEM_DMA_FC |
DMAC_CTRLB_SRC_INCR_INCREMENTING |
DMAC_CTRLB_DST_INCR_INCREMENTING;
/* Pointer to next descriptor */
desc[1].ul_descriptor_addr = (uint32_t) &desc[2];
desc[2].ul_source_addr = (uint32_t) g_dma_buf[2];
desc[2].ul_destination_addr = (uint32_t) g_dma_buf[5];
/*
* Set Buffer Transfer Size
* Source transfer size is set to 32-bit width
* Destination transfer size is set to 32-bit width
*/
desc[2].ul_ctrlA = DMAC_CTRLA_BTSIZE(DMA_BUF_SIZE) |
DMAC_CTRLA_SRC_WIDTH_WORD |
DMAC_CTRLA_DST_WIDTH_WORD;
/*
* Set DMA CTRLB:
* - Source descriptor is fetched from the memory
* - Destination descriptor is fetched from the memory
* - Memory-to-Memory Transfer
* - The source address is incremented
* - The destination address is incremented
*/
desc[2].ul_ctrlB = DMAC_CTRLB_SRC_DSCR_FETCH_FROM_MEM |
DMAC_CTRLB_DST_DSCR_FETCH_FROM_MEM |
DMAC_CTRLB_FC_MEM2MEM_DMA_FC |
DMAC_CTRLB_SRC_INCR_INCREMENTING |
DMAC_CTRLB_DST_INCR_INCREMENTING;
/* The end of LLI */
desc[2].ul_descriptor_addr = 0;
dmac_channel_multi_buf_transfer_init(DMAC, DMA_CH, &desc[0]);
/* Set interrupt */
NVIC_EnableIRQ(DMAC_IRQn);
dmac_enable_interrupt(DMAC, (DMAC_EBCIER_CBTC0 << DMA_CH));
/* Start DMA transfer and wait for finish */
g_xfer_done = 0;
dmac_channel_enable(DMAC, DMA_CH);
while (!g_xfer_done) {
}
/* Verify the transferred data */
for (i = 0; i < DMA_BUF_SIZE; i++) {
if ((g_dma_buf[0][i] != g_dma_buf[3][i]) ||
(g_dma_buf[1][i] != g_dma_buf[4][i]) ||
(g_dma_buf[2][i] != g_dma_buf[5][i])) {
printf("> Test NG.\n\r");
while (1) {
}
}
}
printf("> Test OK.\n\r");
}
/**
* \brief Test DMA single buffer transfer with polling mode.
*/
static void test_single_buf_xfer(void)
{
//! [dmac_define_vars]
uint32_t i;
uint32_t cfg;
dma_transfer_descriptor_t desc;
//! [dmac_define_vars]
printf("\n\rTest single buffer transfer...\n\r");
//! [dmac_define_prepare_buffer]
/** Initialize DMA buffer */
for (i = 0; i < DMA_BUF_SIZE; i++) {
g_dma_buf[0][i] = i;
g_dma_buf[1][i] = 0;
}
//! [dmac_define_prepare_buffer]
/* Initialize and enable DMA controller */
//! [dmac_init_clock]
pmc_enable_periph_clk(ID_DMAC);
//! [dmac_init_clock]
//! [dmac_init_module]
dmac_init(DMAC);
//! [dmac_init_module]
//! [dmac_set_priority]
dmac_set_priority_mode(DMAC, DMAC_PRIORITY_ROUND_ROBIN);
//! [dmac_set_priority]
//! [dmac_enable_module]
dmac_enable(DMAC);
//! [dmac_enable_module]
//! [dmac_configure_channel]
/** Set for channel configuration register */
cfg = DMAC_CFG_SOD_ENABLE | /** Enable stop on done */
DMAC_CFG_AHB_PROT(1) | /** Set AHB Protection */
DMAC_CFG_FIFOCFG_ALAP_CFG; /** FIFO Configuration */
dmac_channel_set_configuration(DMAC, DMA_CH, cfg);
//! [dmac_configure_channel]
//! [dmac_configure_for_single_transfer_1]
/** Initialize single buffer transfer: buffer 0 -> buffer 1 */
desc.ul_source_addr = (uint32_t) g_dma_buf[0];
desc.ul_destination_addr = (uint32_t) g_dma_buf[1];
//! [dmac_configure_for_single_transfer_1]
/*
* Set DMA CTRLA:
* - Set Buffer Transfer Size
* - Source transfer size is set to 32-bit width
* - Destination transfer size is set to 32-bit width
*/
//! [dmac_configure_for_single_transfer_2]
desc.ul_ctrlA = DMAC_CTRLA_BTSIZE(DMA_BUF_SIZE) |
DMAC_CTRLA_SRC_WIDTH_WORD |
DMAC_CTRLA_DST_WIDTH_WORD;
//! [dmac_configure_for_single_transfer_2]
/*
* Set DMA CTRLB:
* - Buffer Descriptor Fetch operation is disabled for the source
* - Buffer Descriptor Fetch operation is disabled for the destination
* - Memory-to-Memory Transfer
* - The source address is incremented
* - The destination address is incremented
*/
//! [dmac_configure_for_single_transfer_3]
desc.ul_ctrlB = DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE |
DMAC_CTRLB_DST_DSCR_FETCH_DISABLE |
DMAC_CTRLB_FC_MEM2MEM_DMA_FC |
DMAC_CTRLB_SRC_INCR_INCREMENTING |
DMAC_CTRLB_DST_INCR_INCREMENTING;
//! [dmac_configure_for_single_transfer_3]
/* No descriptor for single transfer */
//! [dmac_configure_for_single_transfer_4]
desc.ul_descriptor_addr = 0;
dmac_channel_single_buf_transfer_init(DMAC, DMA_CH, &desc);
//! [dmac_configure_for_single_transfer_4]
/* Start DMA transfer and wait for finish */
//! [dmac_start_transfer]
dmac_channel_enable(DMAC, DMA_CH);
//! [dmac_start_transfer]
//! [dmac_wait_for_done]
while (!dmac_channel_is_transfer_done(DMAC, DMA_CH)) {
}
//! [dmac_wait_for_done]
/* Verify the transferred data */
for (i = 0; i < DMA_BUF_SIZE; i++) {
if (g_dma_buf[0][i] != g_dma_buf[1][i]) {
printf("> Test NG.\n\r");
while (1) {
}
}
}
printf("> Test OK\n\r");
}
/**
* \brief ECB mode encryption and decryption test with DMA.
*/
static void ecb_mode_test_dma(void)
{
/* Configure DMAC. */
configure_dmac();
/* Disable DMAC channel. */
dmac_channel_disable(DMAC, AES_DMA_TX_CH);
dmac_channel_disable(DMAC, AES_DMA_RX_CH);
printf("\r\n-----------------------------------\r\n");
printf("- 128bit cryptographic key\r\n");
printf("- ECB cipher mode\r\n");
printf("- DMA mode\r\n");
printf("- input of 4 32bit words with DMA\r\n");
printf("-----------------------------------\r\n");
state = false;
/* Configure the AES. */
g_aes_cfg.encrypt_mode = AES_ENCRYPTION;
g_aes_cfg.key_size = AES_KEY_SIZE_128;
g_aes_cfg.start_mode = AES_IDATAR0_START;
g_aes_cfg.opmode = AES_ECB_MODE;
g_aes_cfg.cfb_size = AES_CFB_SIZE_128;
g_aes_cfg.lod = false;
aes_set_config(AES, &g_aes_cfg);
/* Set the cryptographic key. */
aes_write_key(AES, key128);
/* The initialization vector is not used by the ECB cipher mode. */
/* Write the data to be ciphered by DMA. */
aes_dma_transmit_config(ref_plain_text, AES_EXAMPLE_REFBUF_SIZE);
aes_dma_receive_config(output_data, AES_EXAMPLE_REFBUF_SIZE);
/* Enable DMAC channel. */
dmac_channel_enable(DMAC, AES_DMA_RX_CH);
dmac_channel_enable(DMAC, AES_DMA_TX_CH);
/* Wait for the end of the encryption process. */
while (false == state) {
}
/* Disable DMAC channel. */
dmac_channel_disable(DMAC, AES_DMA_TX_CH);
dmac_channel_disable(DMAC, AES_DMA_RX_CH);
if ((ref_cipher_text_ecb[0] != output_data[0]) ||
(ref_cipher_text_ecb[1] != output_data[1]) ||
(ref_cipher_text_ecb[2] != output_data[2]) ||
(ref_cipher_text_ecb[3] != output_data[3])) {
printf("\r\nKO!!!\r\n");
} else {
printf("\r\nOK!!!\r\n");
}
printf("\r\n-----------------------------------\r\n");
printf("- 128bit cryptographic key\r\n");
printf("- ECB decipher mode\r\n");
printf("- DMA mode\r\n");
printf("- input of 4 32bit words with DMA\r\n");
printf("-----------------------------------\r\n");
state = false;
/* Configure the AES. */
g_aes_cfg.encrypt_mode = AES_DECRYPTION;
g_aes_cfg.key_size = AES_KEY_SIZE_128;
g_aes_cfg.start_mode = AES_IDATAR0_START;
g_aes_cfg.opmode = AES_ECB_MODE;
g_aes_cfg.cfb_size = AES_CFB_SIZE_128;
g_aes_cfg.lod = false;
aes_set_config(AES, &g_aes_cfg);
/* Set the cryptographic key. */
aes_write_key(AES, key128);
/* The initialization vector is not used by the ECB cipher mode. */
/* Write the data to be ciphered by DMA. */
aes_dma_transmit_config(ref_cipher_text_ecb, AES_EXAMPLE_REFBUF_SIZE);
aes_dma_receive_config(output_data, AES_EXAMPLE_REFBUF_SIZE);
/* Enable DMAC channel. */
dmac_channel_enable(DMAC, AES_DMA_RX_CH);
dmac_channel_enable(DMAC, AES_DMA_TX_CH);
/* Wait for the end of the decryption process. */
while (false == state) {
}
/* Disable DMAC channel. */
dmac_channel_disable(DMAC, AES_DMA_TX_CH);
dmac_channel_disable(DMAC, AES_DMA_RX_CH);
/* check the result. */
if ((ref_plain_text[0] != output_data[0]) ||
(ref_plain_text[1] != output_data[1]) ||
(ref_plain_text[2] != output_data[2]) ||
(ref_plain_text[3] != output_data[3])) {
printf("\r\nKO!!!\r\n");
} else {
printf("\r\nOK!!!\r\n");
}
/* Disable DMAC module */
dmac_disable(DMAC);
}
/**
* \brief Test ECB mode encryption and decryption with DMA.
*
* \param test Current test case.
*/
static void run_ecb_mode_test_dma(const struct test_case *test)
{
/* Configure DMAC. */
configure_dmac();
/* Disable DMAC channel. */
dmac_channel_disable(DMAC, AES_DMA_TX_CH);
dmac_channel_disable(DMAC, AES_DMA_RX_CH);
/* Configure the AES. */
g_aes_cfg.encrypt_mode = AES_ENCRYPTION;
g_aes_cfg.key_size = AES_KEY_SIZE_128;
g_aes_cfg.start_mode = AES_DMA_MODE;
g_aes_cfg.opmode = AES_ECB_MODE;
g_aes_cfg.cfb_size = AES_CFB_SIZE_128;
g_aes_cfg.lod = false;
aes_set_config(AES, &g_aes_cfg);
/* Set the cryptographic key. */
aes_write_key(AES, key128);
/* The initialization vector is not used by the ECB cipher mode. */
/* Write the data to be ciphered by DMA. */
aes_dma_transmit_config(ref_plain_text, AES_EXAMPLE_REFBUF_SIZE);
aes_dma_receive_config(output_data, AES_EXAMPLE_REFBUF_SIZE);
/* Enable DMAC channel. */
dmac_channel_enable(DMAC, AES_DMA_RX_CH);
dmac_channel_enable(DMAC, AES_DMA_TX_CH);
/* Wait for the end of the encryption process. */
delay_ms(30);
/* Disable DMAC channel. */
dmac_channel_disable(DMAC, AES_DMA_TX_CH);
dmac_channel_disable(DMAC, AES_DMA_RX_CH);
if ((ref_cipher_text_ecb[0] != output_data[0]) ||
(ref_cipher_text_ecb[1] != output_data[1]) ||
(ref_cipher_text_ecb[2] != output_data[2]) ||
(ref_cipher_text_ecb[3] != output_data[3])) {
flag = false;
} else {
flag = true;
}
test_assert_true(test, flag == true, "ECB mode encryption not work!");
/* Configure the AES. */
g_aes_cfg.encrypt_mode = AES_DECRYPTION;
g_aes_cfg.key_size = AES_KEY_SIZE_128;
g_aes_cfg.start_mode = AES_DMA_MODE;
g_aes_cfg.opmode = AES_ECB_MODE;
g_aes_cfg.cfb_size = AES_CFB_SIZE_128;
g_aes_cfg.lod = false;
aes_set_config(AES, &g_aes_cfg);
/* Set the cryptographic key. */
aes_write_key(AES, key128);
/* The initialization vector is not used by the ECB cipher mode. */
/* Write the data to be ciphered by DMA. */
aes_dma_transmit_config(ref_cipher_text_ecb, AES_EXAMPLE_REFBUF_SIZE);
aes_dma_receive_config(output_data, AES_EXAMPLE_REFBUF_SIZE);
/* Enable DMAC channel. */
dmac_channel_enable(DMAC, AES_DMA_RX_CH);
dmac_channel_enable(DMAC, AES_DMA_TX_CH);
/* Wait for the end of the decryption process. */
delay_ms(30);
/* Disable DMAC channel. */
dmac_channel_disable(DMAC, AES_DMA_TX_CH);
dmac_channel_disable(DMAC, AES_DMA_RX_CH);
/* check the result. */
if ((ref_plain_text[0] != output_data[0]) ||
(ref_plain_text[1] != output_data[1]) ||
(ref_plain_text[2] != output_data[2]) ||
(ref_plain_text[3] != output_data[3])) {
flag = false;
} else {
flag = true;
}
test_assert_true(test, flag == true, "ECB mode decryption not work!");
/* Disable DMAC module */
dmac_disable(DMAC);
}
void channel5_trans_start(u32 srcadr, u32 dstadr, u16 trans_blk){
REG32(DMA_SAR5L) = srcadr;
REG32(DMA_DAR5L) = dstadr;
REG32(DMA_CTL5H) = trans_blk;
dmac_channel_enable(5);
}
void channel0_trans_start(u32 srcadr, u32 dstadr, u16 trans_blk){
DMA_SAR0L = srcadr;
DMA_DAR0L = dstadr;
DMA_CTL0H = trans_blk;
dmac_channel_enable(0);
}
void channel1_trans_start(u32 srcadr, u32 dstadr, u16 trans_blk){
DMA_SAR1L = srcadr;
DMA_DAR1L = dstadr;
DMA_CTL1H = trans_blk;
dmac_channel_enable(1);
}