static int mc_fixup_dpc(u64 dpc_addr) { void *blob = (void *)dpc_addr; int nodeoffset; /* delete any existing ICID pools */ nodeoffset = fdt_path_offset(blob, "/resources/icid_pools"); if (fdt_del_node(blob, nodeoffset) < 0) printf("\nfsl-mc: WARNING: could not delete ICID pool\n"); /* add a new pool */ nodeoffset = fdt_path_offset(blob, "/resources"); if (nodeoffset < 0) { printf("\nfsl-mc: ERROR: DPC is missing /resources\n"); return -EINVAL; } nodeoffset = fdt_add_subnode(blob, nodeoffset, "icid_pools"); nodeoffset = fdt_add_subnode(blob, nodeoffset, "icid_pool@0"); do_fixup_by_path_u32(blob, "/resources/icid_pools/icid_pool@0", "base_icid", FSL_DPAA2_STREAM_ID_START, 1); do_fixup_by_path_u32(blob, "/resources/icid_pools/icid_pool@0", "num", FSL_DPAA2_STREAM_ID_END - FSL_DPAA2_STREAM_ID_START + 1, 1); flush_dcache_range(dpc_addr, dpc_addr + fdt_totalsize(blob)); return 0; }
void ft_cpu_setup(void *blob, bd_t *bd) { sys_info_t sys_info; int off, ndepth = 0; get_sys_info(&sys_info); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency", bd->bi_intfreq, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency", bd->bi_intfreq, 1); do_fixup_by_path_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1); do_fixup_by_path_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1); if (fdt_path_offset(blob, "/plb/opb/ebc") >= 0) do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency", sys_info.freqEBC, 1); else do_fixup_by_path_u32(blob, "/plb/ebc", "clock-frequency", sys_info.freqEBC, 1); fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); /* * Fixup all UART clocks for CPU internal UARTs * (only these UARTs are definitely clocked by gd->arch.uart_clk) * * These UARTs are direct childs of /plb/opb. This code * does not touch any UARTs that are connected to the ebc. */ off = fdt_path_offset(blob, "/plb/opb"); while ((off = fdt_next_node(blob, off, &ndepth)) >= 0) { /* * process all sub nodes and stop when we are back * at the starting depth */ if (ndepth <= 0) break; /* only update direct childs */ if ((ndepth == 1) && (fdt_node_check_compatible(blob, off, "ns16550") == 0)) fdt_setprop(blob, off, "clock-frequency", (void *)&gd->arch.uart_clk, 4); } /* * Fixup all ethernet nodes * Note: aliases in the dts are required for this */ fdt_fixup_ethernet(blob); /* * Fixup all available PCIe nodes by setting the device_type property */ fdt_pcie_setup(blob); }
void ft_board_setup(void *blob, bd_t *bd) { /* bring in eMMC dsr settings */ do_fixup_by_path_u32(blob, "/soc/aips-bus@02100000/usdhc@02198000", "dsr", tqma6_emmc_dsr, 2); tqma6_bb_ft_board_setup(blob, bd); }
void ft_cpu_setup(void *blob, bd_t *bd) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); unsigned int svr = gur_in32(&gur->svr); /* delete crypto node if not on an E-processor */ if (!IS_E_PROCESSOR(svr)) fdt_fixup_crypto_node(blob, 0); #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 else { ccsr_sec_t __iomem *sec; #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT if (fdt_fixup_kaslr(blob)) fdt_fixup_remove_jr(blob); #endif sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); } #endif #ifdef CONFIG_MP ft_fixup_cpu(blob); #endif #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "fsl,ns16550", "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif #ifdef CONFIG_FSL_ESDHC fdt_fixup_esdhc(blob, bd); #endif #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_firmware(blob); #endif #ifndef CONFIG_ARCH_LS1012A fsl_fdt_disable_usb(blob); #endif #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN fdt_fixup_gic(blob); #endif #ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI fdt_fixup_msi(blob); #endif }
void ft_cpu_setup(void *blob, bd_t *bd) { sys_info_t sys_info; get_sys_info(&sys_info); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency", bd->bi_intfreq, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency", bd->bi_intfreq, 1); do_fixup_by_path_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1); do_fixup_by_path_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1); if (fdt_path_offset(blob, "/plb/opb/ebc") >= 0) do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency", sys_info.freqEBC, 1); else do_fixup_by_path_u32(blob, "/plb/ebc", "clock-frequency", sys_info.freqEBC, 1); fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); /* * Setup all baudrates for the UARTs */ do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", gd->uart_clk, 1); /* * Fixup all ethernet nodes * Note: aliases in the dts are required for this */ fdt_fixup_ethernet(blob, bd); /* * Fixup all available PCIe nodes by setting the device_type property */ fdt_pcie_setup(blob); }
void ft_fixup_enet_phy_connect_type(void *fdt) { struct eth_device *dev; struct tsec_private *priv; const char *enet_path, *phy_path; char enet[16]; char phy[16]; int phy_node; int i = 0; uint32_t ph; char *name[3] = { "eTSEC1", "eTSEC2", "eTSEC3" }; for (; i < ARRAY_SIZE(name); i++) { dev = eth_get_dev_by_name(name[i]); if (dev) { sprintf(enet, "ethernet%d", i); sprintf(phy, "enet%d_rgmii_phy", i); } else { continue; } priv = dev->priv; if (priv->flags & TSEC_SGMII) continue; enet_path = fdt_get_alias(fdt, enet); if (!enet_path) continue; phy_path = fdt_get_alias(fdt, phy); if (!phy_path) continue; phy_node = fdt_path_offset(fdt, phy_path); if (phy_node < 0) continue; ph = fdt_create_phandle(fdt, phy_node); if (ph) do_fixup_by_path_u32(fdt, enet_path, "phy-handle", ph, 1); do_fixup_by_path(fdt, enet_path, "phy-connection-type", phy_string_for_interface( PHY_INTERFACE_MODE_RGMII_ID), sizeof(phy_string_for_interface( PHY_INTERFACE_MODE_RGMII_ID)), 1); } }
void ft_cpu_setup(void *blob, bd_t *bd) { int off; int val; const char *sysclk_path; struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); unsigned int svr; svr = in_be32(&gur->svr); unsigned long busclk = get_bus_freq(0); /* delete crypto node if not on an E-processor */ if (!IS_E_PROCESSOR(svr)) fdt_fixup_crypto_node(blob, 0); #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 else { ccsr_sec_t __iomem *sec; sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); } #endif off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); while (off != -FDT_ERR_NOTFOUND) { val = gd->cpu_clk; fdt_setprop(blob, off, "clock-frequency", &val, 4); off = fdt_node_offset_by_prop_value(blob, off, "device_type", "cpu", 4); } do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", busclk, 1); ft_fixup_enet_phy_connect_type(blob); #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64", "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif sysclk_path = fdt_get_alias(blob, "sysclk"); if (sysclk_path) do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0", "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); #if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT) #define UBOOT_HEAD_LEN 0x1000 /* * Reserved memory in SD boot deep sleep case. * Second stage uboot binary and malloc space should be reserved. * If the memory they occupied has not been reserved, then this * space would be used by kernel and overwritten in uboot when * deep sleep resume, which cause deep sleep failed. * Since second uboot binary has a head, that space need to be * reserved either(assuming its size is less than 0x1000). */ off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN, CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE + UBOOT_HEAD_LEN); if (off < 0) printf("Failed to reserve memory for SD boot deep sleep: %s\n", fdt_strerror(off)); #endif #if defined(CONFIG_FSL_ESDHC) fdt_fixup_esdhc(blob, bd); #endif /* * platform bus clock = system bus clock/2 * Here busclk = system bus clock * We are using the platform bus clock as 1588 Timer reference * clock source select */ do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer", "timer-frequency", busclk / 2, 1); /* * clock-freq should change to clock-frequency and * flexcan-v1.0 should change to p1010-flexcan respectively * in the future. */ do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0", "clock_freq", busclk / 2, 1); do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0", "clock-frequency", busclk / 2, 1); do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan", "clock-frequency", busclk / 2, 1); #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT, CONFIG_SYS_IFC_ADDR); fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); #else off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT, QSPI0_BASE_ADDR); fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT, DSPI1_BASE_ADDR); fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); #endif }