void ft_board_setup(void *blob, bd_t *bd) { do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency", bd->bi_busfreq / 4, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency", bd->bi_intfreq, 1); do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", bd->bi_busfreq, 1); fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize); #ifdef CONFIG_PCI1 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); #endif #ifdef CONFIG_PCIE1 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); #endif #ifdef CONFIG_PCIE2 ft_fsl_pci_setup(blob, "pci2", &pcie2_hose); #endif }
void ft_cpu_setup(void *blob, bd_t *bd) { sys_info_t sys_info; int off, ndepth = 0; get_sys_info(&sys_info); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency", bd->bi_intfreq, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency", bd->bi_intfreq, 1); do_fixup_by_path_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1); do_fixup_by_path_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1); if (fdt_path_offset(blob, "/plb/opb/ebc") >= 0) do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency", sys_info.freqEBC, 1); else do_fixup_by_path_u32(blob, "/plb/ebc", "clock-frequency", sys_info.freqEBC, 1); fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); /* * Fixup all UART clocks for CPU internal UARTs * (only these UARTs are definitely clocked by gd->arch.uart_clk) * * These UARTs are direct childs of /plb/opb. This code * does not touch any UARTs that are connected to the ebc. */ off = fdt_path_offset(blob, "/plb/opb"); while ((off = fdt_next_node(blob, off, &ndepth)) >= 0) { /* * process all sub nodes and stop when we are back * at the starting depth */ if (ndepth <= 0) break; /* only update direct childs */ if ((ndepth == 1) && (fdt_node_check_compatible(blob, off, "ns16550") == 0)) fdt_setprop(blob, off, "clock-frequency", (void *)&gd->arch.uart_clk, 4); } /* * Fixup all ethernet nodes * Note: aliases in the dts are required for this */ fdt_fixup_ethernet(blob); /* * Fixup all available PCIe nodes by setting the device_type property */ fdt_pcie_setup(blob); }
void ft_cpu_setup(void *blob, bd_t *bd) { immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; int spridr = immr->sysconf.spridr; /* * delete crypto node if not on an E-processor * initial revisions of the MPC834xE/6xE have the original SEC 2.0. * EA revisions got the SEC uprevved to 2.4 but since the default device * tree contains SEC 2.0 properties we uprev them here. */ if (!IS_E_PROCESSOR(spridr)) fdt_fixup_crypto_node(blob, 0); else if (IS_E_PROCESSOR(spridr) && (SPR_FAMILY(spridr) == SPR_834X_FAMILY || SPR_FAMILY(spridr) == SPR_836X_FAMILY) && REVID_MAJOR(spridr) >= 2) fdt_fixup_crypto_node(blob, 0x0204); #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\ defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5) fdt_fixup_ethernet(blob); #endif do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency", (bd->bi_busfreq / 4), 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency", gd->core_clk, 1); do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_compat_u32(blob, "fsl,soc", "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_compat_u32(blob, "fsl,soc", "clock-frequency", bd->bi_busfreq, 1); do_fixup_by_compat_u32(blob, "fsl,immr", "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_compat_u32(blob, "fsl,immr", "clock-frequency", bd->bi_busfreq, 1); #ifdef CONFIG_QE ft_qe_setup(blob); #endif #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); #if defined(CONFIG_BOOTCOUNT_LIMIT) fdt_fixup_muram (blob); #endif }
void ft_cpu_setup(void *blob, bd_t *bd) { #ifdef CONFIG_MP int off; u32 bootpg = determine_mp_bootpg(NULL); #endif do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency", bd->bi_busfreq / 4, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency", bd->bi_intfreq, 1); do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", bd->bi_busfreq, 1); #if defined(CONFIG_MPC8641) do_fixup_by_compat_u32(blob, "fsl,mpc8641-localbus", "bus-frequency", gd->arch.lbc_clk, 1); #endif do_fixup_by_compat_u32(blob, "fsl,elbc", "bus-frequency", gd->arch.lbc_clk, 1); fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) \ || defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) fdt_fixup_ethernet(blob); #endif #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif #ifdef CONFIG_MP /* Reserve the boot page so OSes dont use it */ off = fdt_add_mem_rsv(blob, bootpg, (u64)4096); if (off < 0) printf("%s: %s\n", __FUNCTION__, fdt_strerror(off)); ft_fixup_num_cores(blob); #endif #ifdef CONFIG_SYS_SRIO ft_srio_setup(blob); #endif }
void ft_qe_setup(void *blob) { do_fixup_by_prop_u32(blob, "device_type", "qe", 4, "bus-frequency", gd->arch.qe_clk, 1); do_fixup_by_prop_u32(blob, "device_type", "qe", 4, "brg-frequency", gd->arch.brg_clk, 1); do_fixup_by_compat_u32(blob, "fsl,qe", "clock-frequency", gd->arch.qe_clk, 1); do_fixup_by_compat_u32(blob, "fsl,qe", "bus-frequency", gd->arch.qe_clk, 1); do_fixup_by_compat_u32(blob, "fsl,qe", "brg-frequency", gd->arch.brg_clk, 1); do_fixup_by_compat_u32(blob, "fsl,qe-gtm", "clock-frequency", gd->arch.qe_clk / 2, 1); fdt_fixup_qe_firmware(blob); }
void ft_cpu_setup(void *blob, bd_t *bd) { do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency", get_tbclk(), 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency", bd->bi_intfreq, 1); do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency", gd->arch.brg_clk, 1); /* Fixup ethernet MAC addresses */ fdt_fixup_ethernet(blob); fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); }
void ft_cpu_setup(void *blob, bd_t *bd) { #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) fdt_fixup_ethernet(blob, bd); #endif do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency", (bd->bi_busfreq / 4), 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency", gd->core_clk, 1); do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_compat_u32(blob, "fsl,soc", "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_compat_u32(blob, "fsl,soc", "clock-frequency", bd->bi_busfreq, 1); do_fixup_by_compat_u32(blob, "fsl,immr", "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_compat_u32(blob, "fsl,immr", "clock-frequency", bd->bi_busfreq, 1); #ifdef CONFIG_QE ft_qe_setup(blob); #endif #ifdef CFG_NS16550 do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", bd->bi_busfreq, 1); #endif #ifdef CONFIG_CPM2 do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart", "current-speed", bd->bi_baudrate, 1); do_fixup_by_compat_u32(blob, "fsl,cpm2-brg", "clock-frequency", bd->bi_brgfreq, 1); #endif fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); }
void ft_cpu_setup(void *blob, bd_t *bd) { sys_info_t sys_info; get_sys_info(&sys_info); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency", bd->bi_intfreq, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency", bd->bi_intfreq, 1); do_fixup_by_path_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1); do_fixup_by_path_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1); if (fdt_path_offset(blob, "/plb/opb/ebc") >= 0) do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency", sys_info.freqEBC, 1); else do_fixup_by_path_u32(blob, "/plb/ebc", "clock-frequency", sys_info.freqEBC, 1); fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); /* * Setup all baudrates for the UARTs */ do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", gd->uart_clk, 1); /* * Fixup all ethernet nodes * Note: aliases in the dts are required for this */ fdt_fixup_ethernet(blob, bd); /* * Fixup all available PCIe nodes by setting the device_type property */ fdt_pcie_setup(blob); }
void ft_cpu_setup(void *blob, bd_t *bd) { do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency", bd->bi_busfreq / 4, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency", bd->bi_intfreq, 1); do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", bd->bi_busfreq, 1); fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) \ || defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) fdt_fixup_ethernet(blob, bd); #endif #ifdef CFG_NS16550 do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", bd->bi_busfreq, 1); #endif }
void ft_pci_setup(void *blob, bd_t *bd) { do_fixup_by_prop_u32(blob, "device_type", "pci", 4, "clock-frequency", bd->pci_clk, 1); }
void ft_cpu_setup(void *blob, bd_t *bd) { int off; int val; const char *sysclk_path; struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); unsigned int svr; svr = in_be32(&gur->svr); unsigned long busclk = get_bus_freq(0); /* delete crypto node if not on an E-processor */ if (!IS_E_PROCESSOR(svr)) fdt_fixup_crypto_node(blob, 0); #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 else { ccsr_sec_t __iomem *sec; sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); } #endif off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); while (off != -FDT_ERR_NOTFOUND) { val = gd->cpu_clk; fdt_setprop(blob, off, "clock-frequency", &val, 4); off = fdt_node_offset_by_prop_value(blob, off, "device_type", "cpu", 4); } do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", busclk, 1); ft_fixup_enet_phy_connect_type(blob); #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64", "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif sysclk_path = fdt_get_alias(blob, "sysclk"); if (sysclk_path) do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0", "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); #if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT) #define UBOOT_HEAD_LEN 0x1000 /* * Reserved memory in SD boot deep sleep case. * Second stage uboot binary and malloc space should be reserved. * If the memory they occupied has not been reserved, then this * space would be used by kernel and overwritten in uboot when * deep sleep resume, which cause deep sleep failed. * Since second uboot binary has a head, that space need to be * reserved either(assuming its size is less than 0x1000). */ off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN, CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE + UBOOT_HEAD_LEN); if (off < 0) printf("Failed to reserve memory for SD boot deep sleep: %s\n", fdt_strerror(off)); #endif #if defined(CONFIG_FSL_ESDHC) fdt_fixup_esdhc(blob, bd); #endif /* * platform bus clock = system bus clock/2 * Here busclk = system bus clock * We are using the platform bus clock as 1588 Timer reference * clock source select */ do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer", "timer-frequency", busclk / 2, 1); /* * clock-freq should change to clock-frequency and * flexcan-v1.0 should change to p1010-flexcan respectively * in the future. */ do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0", "clock_freq", busclk / 2, 1); do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0", "clock-frequency", busclk / 2, 1); do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan", "clock-frequency", busclk / 2, 1); #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT, CONFIG_SYS_IFC_ADDR); fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); #else off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT, QSPI0_BASE_ADDR); fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT, DSPI1_BASE_ADDR); fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); #endif }
void ft_cpu_setup(void *blob, bd_t *bd) { immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; int spridr = immr->sysconf.spridr; /* * delete crypto node if not on an E-processor * initial revisions of the MPC834xE/6xE have the original SEC 2.0. * EA revisions got the SEC uprevved to 2.4 but since the default device * tree contains SEC 2.0 properties we uprev them here. */ if (!IS_E_PROCESSOR(spridr)) fdt_fixup_crypto_node(blob, 0); else if (IS_E_PROCESSOR(spridr) && (SPR_FAMILY(spridr) == SPR_834X_FAMILY || SPR_FAMILY(spridr) == SPR_836X_FAMILY) && REVID_MAJOR(spridr) >= 2) fdt_fixup_crypto_node(blob, 0x0204); #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\ defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5) fdt_fixup_ethernet(blob); #ifdef CONFIG_MPC8313 /* * mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1 * h/w (see AN3545). The base device tree in use has rev. 1 ID numbers, * so if on Rev. 2 (and higher) h/w, we fix them up here */ if (REVID_MAJOR(immr->sysconf.spridr) >= 2) { int nodeoffset, path; const char *prop; nodeoffset = fdt_path_offset(blob, "/aliases"); if (nodeoffset >= 0) { #if defined(CONFIG_HAS_ETH0) prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL); if (prop) { u32 tmp[] = { 32, 0x8, 33, 0x8, 34, 0x8 }; path = fdt_path_offset(blob, prop); prop = fdt_getprop(blob, path, "interrupts", NULL); if (prop) fdt_setprop(blob, path, "interrupts", &tmp, sizeof(tmp)); } #endif #if defined(CONFIG_HAS_ETH1) prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL); if (prop) { u32 tmp[] = { 35, 0x8, 36, 0x8, 37, 0x8 }; path = fdt_path_offset(blob, prop); prop = fdt_getprop(blob, path, "interrupts", NULL); if (prop) fdt_setprop(blob, path, "interrupts", &tmp, sizeof(tmp)); } #endif } } #endif #endif do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency", (bd->bi_busfreq / 4), 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency", gd->arch.core_clk, 1); do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_compat_u32(blob, "fsl,soc", "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_compat_u32(blob, "fsl,soc", "clock-frequency", bd->bi_busfreq, 1); do_fixup_by_compat_u32(blob, "fsl,immr", "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_compat_u32(blob, "fsl,immr", "clock-frequency", bd->bi_busfreq, 1); #ifdef CONFIG_QE ft_qe_setup(blob); #endif #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); #if defined(CONFIG_BOOTCOUNT_LIMIT) && \ (defined(CONFIG_QE) && !defined(CONFIG_MPC831x)) fdt_fixup_muram (blob); #endif }