int ovl2mem_trigger(int blocking, void *callback, unsigned int userdata)
{
int ret = -1;
DISPFUNC();
if(pgc->need_trigger_path == 0)
{
DISPMSG("ovl2mem_trigger do not trigger\n");
return ret;
}
_ovl2mem_path_lock(__func__);
dpmgr_path_start(pgc->dpmgr_handle, ovl2mem_cmdq_enabled());
dpmgr_path_trigger(pgc->dpmgr_handle, pgc->cmdq_handle_config, ovl2mem_cmdq_enabled());
cmdqRecWait(pgc->cmdq_handle_config, CMDQ_EVENT_DISP_WDMA1_EOF);
dpmgr_path_stop(pgc->dpmgr_handle, ovl2mem_cmdq_enabled());
///cmdqRecDumpCommand(pgc->cmdq_handle_config);
cmdqRecFlushAsyncCallback(pgc->cmdq_handle_config, ovl2mem_callback, atomic_read(&g_trigger_ticket));
cmdqRecReset(pgc->cmdq_handle_config);
pgc->need_trigger_path = 0;
atomic_add(1, &g_trigger_ticket );
_ovl2mem_path_unlock(__func__);
DISPMSG("ovl2mem_trigger done %d\n", get_ovl2mem_ticket());
return ret;
}
int ovl2mem_trigger(int blocking, void *callback, unsigned int userdata)
{
int ret = -1;
int fence_idx = 0;
int layid = 0;
DISPFUNC();
if(pgc->need_trigger_path == 0)
{
DISPMSG("ovl2mem_trigger do not trigger\n");
if ((atomic_read(&g_trigger_ticket) - atomic_read(&g_release_ticket)) == 1)
{
DISPMSG("ovl2mem_trigger(%x), configue input, but does not config output!!\n", pgc->session);
for(layid = 0; layid < (HW_OVERLAY_COUNT + 1); layid++)
{
fence_idx = mtkfb_query_idx_by_ticket(pgc->session, layid, atomic_read(&g_trigger_ticket));
if(fence_idx >=0)
{
mtkfb_release_fence(pgc->session, layid, fence_idx);
}
}
}
return ret;
}
_ovl2mem_path_lock(__func__);
dpmgr_path_start(pgc->dpmgr_handle, ovl2mem_cmdq_enabled());
dpmgr_path_trigger(pgc->dpmgr_handle, pgc->cmdq_handle_config, ovl2mem_cmdq_enabled());
cmdqRecWait(pgc->cmdq_handle_config, CMDQ_EVENT_DISP_WDMA1_EOF);
dpmgr_path_stop(pgc->dpmgr_handle, ovl2mem_cmdq_enabled());
///cmdqRecDumpCommand(pgc->cmdq_handle_config);
cmdqRecFlushAsyncCallback(pgc->cmdq_handle_config, ovl2mem_callback, atomic_read(&g_trigger_ticket));
cmdqRecReset(pgc->cmdq_handle_config);
pgc->need_trigger_path = 0;
atomic_add(1, &g_trigger_ticket );
_ovl2mem_path_unlock(__func__);
dprec_logger_frame_seq_begin(pgc->session, mtkfb_query_frm_seq_by_addr(pgc->session, 0, 0));
DISPMSG("ovl2mem_trigger ovl2mem_seq %d-seq %d\n", get_ovl2mem_ticket(), mtkfb_query_frm_seq_by_addr(pgc->session, 0, 0));
return ret;
}
static int _trigger_overlay_engine(void)
{
// maybe we need a simple merge mechanism for CPU config.
dpmgr_path_trigger(pgc->ovl2mem_path_handle, NULL, ext_disp_use_cmdq);
}
static int _trigger_display_interface(int blocking, void *callback, unsigned int userdata)
{
///EXT_DISP_FUNC();
int i = 0;
bool reg_flush = false;
if(_should_wait_path_idle())
{
dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ/2);
}
if(_should_update_lcm())
{
extd_drv_update(pgc->plcm, 0, 0, pgc->plcm->params->width, pgc->plcm->params->height, 0);
}
if(_should_start_path())
{
reg_flush = true;
dpmgr_path_start(pgc->dpmgr_handle, ext_disp_cmdq_enabled());
MMProfileLogEx(ddp_mmp_get_events()->Extd_State, MMProfileFlagPulse, Trigger, 1);
}
if(_should_trigger_path())
{
// trigger_loop_handle is used only for build trigger loop, which should always be NULL for config thread
dpmgr_path_trigger(pgc->dpmgr_handle, NULL, ext_disp_cmdq_enabled());
}
if(_should_set_cmdq_dirty())
{
_cmdq_set_config_handle_dirty();
}
///if(reg_flush == false)
{
#if 0
if(reg_flush == false)
{
if(_should_insert_wait_frame_done_token())
{
_cmdq_insert_wait_frame_done_token();
}
}
if(_should_flush_cmdq_config_handle())
{
_cmdq_flush_config_handle(reg_flush);
}
if(_should_reset_cmdq_config_handle())
{
_cmdq_reset_config_handle();
}
if(reg_flush == true)
{
if(_should_insert_wait_frame_done_token())
{
_cmdq_insert_wait_frame_done_token();
}
}
///cmdqRecDumpCommand(cmdqRecHandle handle)
#else
if(_should_flush_cmdq_config_handle())
{
if(reg_flush)
{
MMProfileLogEx(ddp_mmp_get_events()->Extd_State, MMProfileFlagPulse, Trigger, 2);
}
if(_should_start_path())
{
EXT_DISP_LOG("Wait Main Display Vsync\n");
disp_session_vsync_config vsync_config;
primary_display_wait_for_vsync(&vsync_config);
}
_cmdq_flush_config_handle(blocking, callback, userdata);
}
if(_should_reset_cmdq_config_handle())
{
_cmdq_reset_config_handle();
}
if(_should_insert_wait_frame_done_token())
{
_cmdq_insert_wait_frame_done_token();
}
#endif
}
return 0;
}
static void _cmdq_build_trigger_loop(void)
{
int ret = 0;
cmdqRecCreate(CMDQ_SCENARIO_TRIGGER_LOOP, &(pgc->cmdq_handle_trigger));
EXT_DISP_LOG("ext_disp path trigger thread cmd handle=%p\n", pgc->cmdq_handle_trigger);
cmdqRecReset(pgc->cmdq_handle_trigger);
if(ext_disp_is_video_mode())
{
// wait and clear stream_done, HW will assert mutex enable automatically in frame done reset.
// todo: should let dpmanager to decide wait which mutex's eof.
ret = cmdqRecWait(pgc->cmdq_handle_trigger, dpmgr_path_get_mutex(pgc->dpmgr_handle) + CMDQ_EVENT_MUTEX0_STREAM_EOF); ///dpmgr_path_get_mutex(pgc->dpmgr_handle)
// for some module(like COLOR) to read hw register to GPR after frame done
dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_AFTER_STREAM_EOF);
}
else
{
// DSI command mode doesn't have mutex_stream_eof, need use CMDQ token instead
ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_DIRTY);
//ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_MDP_DSI0_TE_SOF);
// for operations before frame transfer, such as waiting for DSI TE
dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_BEFORE_STREAM_SOF);
// cleat frame done token, now the config thread will not allowed to config registers.
// remember that config thread's priority is higher than trigger thread, so all the config queued before will be applied then STREAM_EOF token be cleared
// this is what CMDQ did as "Merge"
ret = cmdqRecClearEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_STREAM_EOF);
// enable mutex, only cmd mode need this
// this is what CMDQ did as "Trigger"
dpmgr_path_trigger(pgc->dpmgr_handle, pgc->cmdq_handle_trigger, CMDQ_ENABLE);
//ret = cmdqRecWrite(pgc->cmdq_handle_trigger, (unsigned int)(DISP_REG_CONFIG_MUTEX_EN(0))&0x1fffffff, 1, ~0);
// waiting for frame done, because we can't use mutex stream eof here, so need to let dpmanager help to decide which event to wait
// most time we wait rdmax frame done event.
ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_DISP_RDMA1_EOF);
dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_WAIT_STREAM_EOF_EVENT);
// dsi is not idle rightly after rdma frame done, so we need to polling about 1us for dsi returns to idle
// do not polling dsi idle directly which will decrease CMDQ performance
dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_CHECK_IDLE_AFTER_STREAM_EOF);
// for some module(like COLOR) to read hw register to GPR after frame done
dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_AFTER_STREAM_EOF);
// polling DSI idle
//ret = cmdqRecPoll(pgc->cmdq_handle_trigger, 0x1401b00c, 0, 0x80000000);
// polling wdma frame done
//ret = cmdqRecPoll(pgc->cmdq_handle_trigger, 0x140060A0, 1, 0x1);
// now frame done, config thread is allowed to config register now
ret = cmdqRecSetEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_STREAM_EOF);
// RUN forever!!!!
BUG_ON(ret < 0);
}
// dump trigger loop instructions to check whether dpmgr_path_build_cmdq works correctly
cmdqRecDumpCommand(pgc->cmdq_handle_trigger);
EXT_DISP_LOG("ext display BUILD cmdq trigger loop finished\n");
return;
}
