static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
unsigned long pck_req, unsigned long *fck, int *lck_div,
int *pck_div)
{
struct dsi_clock_info dsi_cinfo;
struct dispc_clock_info dispc_cinfo;
int r;
r = dsi_pll_calc_clock_div_pck(is_tft, pck_req, &dsi_cinfo,
&dispc_cinfo);
if (r)
return r;
r = dsi_pll_set_clock_div(&dsi_cinfo);
if (r)
return r;
dss_select_dispc_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC);
r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
if (r)
return r;
*fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
*lck_div = dispc_cinfo.lck_div;
*pck_div = dispc_cinfo.pck_div;
return 0;
}
static int dpi_set_dsi_clk(enum omap_channel channel,
unsigned long pck_req, unsigned long *fck, int *lck_div,
int *pck_div)
{
struct dpi_clk_calc_ctx ctx;
int r;
bool ok;
ok = dpi_dsi_clk_calc(pck_req, &ctx);
if (!ok)
return -EINVAL;
r = dsi_pll_set_clock_div(dpi.dsidev, &ctx.dsi_cinfo);
if (r)
return r;
dss_select_lcd_clk_source(channel,
dpi_get_alt_clk_src(channel));
dpi.mgr_config.clock_info = ctx.dispc_cinfo;
*fck = ctx.dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
*lck_div = ctx.dispc_cinfo.lck_div;
*pck_div = ctx.dispc_cinfo.pck_div;
return 0;
}
static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
unsigned long pck_req, unsigned long *fck, int *lck_div,
int *pck_div)
{
struct dsi_clock_info dsi_cinfo;
struct dispc_clock_info dispc_cinfo;
int r;
r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft, pck_req,
&dsi_cinfo, &dispc_cinfo);
if (r)
return r;
r = dsi_pll_set_clock_div(dpi.dsidev, &dsi_cinfo);
if (r)
return r;
dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
if (r)
return r;
*fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
*lck_div = dispc_cinfo.lck_div;
*pck_div = dispc_cinfo.pck_div;
return 0;
}
static int dpi_set_dsi_clk(bool is_tft, unsigned long pck_req,
unsigned long *fck, int *lck_div, int *pck_div)
{
struct dsi_clock_info dsi_cinfo;
struct dispc_clock_info dispc_cinfo;
int r;
r = dsi_pll_calc_clock_div_pck(is_tft, pck_req, &dsi_cinfo,
&dispc_cinfo);
if (r)
return r;
r = dsi_pll_set_clock_div(&dsi_cinfo);
if (r)
return r;
dss_select_clk_source(0, 1);
r = dispc_set_clock_div(&dispc_cinfo);
if (r)
return r;
*fck = dsi_cinfo.dsi1_pll_fclk;
*lck_div = dispc_cinfo.lck_div;
*pck_div = dispc_cinfo.pck_div;
return 0;
}
static int dpi_set_dsi_clk(enum omap_channel channel, bool is_tft,
unsigned long pck_req, unsigned long *pck)
{
struct dsi_clock_info dsi_cinfo;
struct dispc_clock_info dispc_cinfo;
int r;
enum omap_dsi_index ix;
DSSDBG("DPI clk source is DSI PLL\n");
ix = (channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
if (!cpu_is_omap44xx()) {
r = dsi_pll_calc_clock_div_pck(ix, is_tft,
pck_req, &dsi_cinfo, &dispc_cinfo);
if (r)
return r;
} else {
dsi_cinfo.regn = 16;
dsi_cinfo.regm = 115;
dsi_cinfo.regm_dispc = 3;
dsi_cinfo.regm_dsi = 3;
dsi_cinfo.use_dss2_fck = true;
r = dsi_calc_clock_rates(channel, &dsi_cinfo);
DSSDBG("dpi_set_dsi_clk: dsi_calc_clock_rates=%d\n", r);
if (r)
return r;
dispc_find_clk_divs(is_tft, pck_req,
dsi_cinfo.dsi_pll_dispc_fclk, &dispc_cinfo);
}
r = dsi_pll_set_clock_div(ix, &dsi_cinfo);
DSSDBG("dpi_set_dsi_clk: dsi_pll_set_clock_div=%d\n", r);
if (r)
return r;
if (cpu_is_omap44xx()){
dss_select_dispc_clk_source(ix, (ix == DSI1) ?
DSS_SRC_PLL1_CLK1 : DSS_SRC_PLL2_CLK1);
dss_select_lcd_clk_source(ix, (ix == DSI1) ?
DSS_SRC_PLL1_CLK1 : DSS_SRC_PLL2_CLK1);
}else{
dss_select_dispc_clk_source(ix, DSS_SRC_DSI1_PLL_FCLK);
}
dispc_set_clock_div(channel, &dispc_cinfo);
*pck = dispc_cinfo.pck;
return 0;
}
static int dpi_set_dsi_clk(int lcd_channel_ix, bool is_tft,
unsigned long pck_req,
unsigned long *fck, int *lck_div, int *pck_div)
{
struct dsi_clock_info dsi_cinfo;
struct dispc_clock_info dispc_cinfo;
int r;
printk(KERN_INFO "DPI set dsi clk");
if (!cpu_is_omap44xx()) {
r = dsi_pll_calc_clock_div_pck(lcd_channel_ix, is_tft,
pck_req, &dsi_cinfo, &dispc_cinfo);
if (r)
return r;
} else {
dispc_cinfo.lck_div = 1;
dispc_cinfo.pck_div = 4;
dsi_cinfo.regn = 19;
dsi_cinfo.regm = 150;
dsi_cinfo.regm3 = 4;
dsi_cinfo.regm4 = 4;
dsi_cinfo.use_dss2_fck = true;
dsi_cinfo.highfreq = 0;
dsi_calc_clock_rates(&dsi_cinfo);
}
r = dsi_pll_set_clock_div(lcd_channel_ix, &dsi_cinfo);
if (r)
return r;
if (cpu_is_omap44xx())
dss_select_clk_source_dsi(lcd_channel_ix, 1, 1);
else
dss_select_clk_source(0, 1);
r = dispc_set_clock_div(lcd_channel_ix, &dispc_cinfo);
if (r)
return r;
*fck = dsi_cinfo.dsi1_pll_fclk;
*lck_div = dispc_cinfo.lck_div;
*pck_div = dispc_cinfo.pck_div;
return 0;
}
