static void sdi_display_disable(struct omap_dss_device *dssdev) { struct omap_overlay_manager *mgr = sdi.output.manager; dss_mgr_disable(mgr); dss_sdi_disable(); dispc_runtime_put(); regulator_disable(sdi.vdds_sdi_reg); }
static void sdi_display_disable(struct omap_dss_device *dssdev) { struct sdi_device *sdi = dssdev_to_sdi(dssdev); dss_mgr_disable(&sdi->output); dss_sdi_disable(sdi->dss); dispc_runtime_put(sdi->dss->dispc); regulator_disable(sdi->vdds_sdi_reg); }
void omapdss_sdi_display_disable(struct omap_dss_device *dssdev) { dssdev->manager->disable(dssdev->manager); dss_sdi_disable(); dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); regulator_disable(sdi.vdds_sdi_reg); omap_dss_stop_device(dssdev); }
void omapdss_sdi_display_disable(struct omap_dss_device *dssdev) { dss_mgr_disable(dssdev->manager); dss_sdi_disable(); dispc_runtime_put(); dss_runtime_put(); regulator_disable(sdi.vdds_sdi_reg); omap_dss_stop_device(dssdev); }
static int sdi_display_suspend(struct omap_dss_device *dssdev) { if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) return -EINVAL; if (dssdev->driver->suspend) dssdev->driver->suspend(dssdev); /* TODO: change here if LCD2 support is needed */ dispc_enable_lcd_out(OMAP_DSS_CHANNEL_LCD, 0); dss_sdi_disable(); dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED; return 0; }
static int sdi_display_suspend(struct omap_display *display) { if (display->state != OMAP_DSS_DISPLAY_ACTIVE) return -EINVAL; if (display->panel->suspend) display->panel->suspend(display); dispc_enable_lcd_out(0); dss_sdi_disable(); dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); sdi_pad_config(display, 0); twl4030_disable_regulator(RES_VAUX1); display->state = OMAP_DSS_DISPLAY_SUSPENDED; return 0; }
static void sdi_display_disable(struct omap_display *display) { if (display->state == OMAP_DSS_DISPLAY_DISABLED) return; if (display->state == OMAP_DSS_DISPLAY_SUSPENDED) { if (sdi_display_resume(display)) return; } display->panel->disable(display); dispc_enable_lcd_out(0); dss_sdi_disable(); dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); sdi_pad_config(display, 0); twl4030_disable_regulator(RES_VAUX1); display->state = OMAP_DSS_DISPLAY_DISABLED; }
static void sdi_display_disable(struct omap_dss_device *dssdev) { if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED) return; if (dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED) if (sdi_display_resume(dssdev)) return; if (dssdev->driver->disable) dssdev->driver->disable(dssdev); /* TODO: change here if LCD2 support is needed */ dispc_enable_lcd_out(OMAP_DSS_CHANNEL_LCD, 0); dss_sdi_disable(); dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); dssdev->state = OMAP_DSS_DISPLAY_DISABLED; omap_dss_stop_device(dssdev); }
int omapdss_sdi_display_enable(struct omap_dss_device *dssdev) { struct omap_video_timings *t = &dssdev->panel.timings; struct dss_clock_info dss_cinfo; struct dispc_clock_info dispc_cinfo; u16 lck_div, pck_div; unsigned long fck; unsigned long pck; int r; if (dssdev->manager == NULL) { DSSERR("failed to enable display: no manager\n"); return -ENODEV; } r = omap_dss_start_device(dssdev); if (r) { DSSERR("failed to start device\n"); goto err_start_dev; } r = regulator_enable(sdi.vdds_sdi_reg); if (r) goto err_reg_enable; r = dss_runtime_get(); if (r) goto err_get_dss; r = dispc_runtime_get(); if (r) goto err_get_dispc; sdi_basic_init(dssdev); /* */ dssdev->panel.config |= OMAP_DSS_LCD_RF | OMAP_DSS_LCD_ONOFF; dispc_mgr_set_pol_freq(dssdev->manager->id, dssdev->panel.config, dssdev->panel.acbi, dssdev->panel.acb); r = dss_calc_clock_div(1, t->pixel_clock * 1000, &dss_cinfo, &dispc_cinfo); if (r) goto err_calc_clock_div; fck = dss_cinfo.fck; lck_div = dispc_cinfo.lck_div; pck_div = dispc_cinfo.pck_div; pck = fck / lck_div / pck_div / 1000; if (pck != t->pixel_clock) { DSSWARN("Could not find exact pixel clock. Requested %d kHz, " "got %lu kHz\n", t->pixel_clock, pck); t->pixel_clock = pck; } dispc_mgr_set_lcd_timings(dssdev->manager->id, t); r = dss_set_clock_div(&dss_cinfo); if (r) goto err_set_dss_clock_div; r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo); if (r) goto err_set_dispc_clock_div; dss_sdi_init(dssdev->phy.sdi.datapairs); r = dss_sdi_enable(); if (r) goto err_sdi_enable; mdelay(2); r = dss_mgr_enable(dssdev->manager); if (r) goto err_mgr_enable; return 0; err_mgr_enable: dss_sdi_disable(); err_sdi_enable: err_set_dispc_clock_div: err_set_dss_clock_div: err_calc_clock_div: dispc_runtime_put(); err_get_dispc: dss_runtime_put(); err_get_dss: regulator_disable(sdi.vdds_sdi_reg); err_reg_enable: omap_dss_stop_device(dssdev); err_start_dev: return r; }
static int sdi_display_enable(struct omap_dss_device *dssdev) { struct sdi_device *sdi = dssdev_to_sdi(dssdev); struct videomode *vm = &sdi->vm; unsigned long fck; struct dispc_clock_info dispc_cinfo; unsigned long pck; int r; if (!sdi->output.dispc_channel_connected) { DSSERR("failed to enable display: no output/manager\n"); return -ENODEV; } r = regulator_enable(sdi->vdds_sdi_reg); if (r) goto err_reg_enable; r = dispc_runtime_get(sdi->dss->dispc); if (r) goto err_get_dispc; /* 15.5.9.1.2 */ vm->flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE | DISPLAY_FLAGS_SYNC_POSEDGE; r = sdi_calc_clock_div(sdi, vm->pixelclock, &fck, &dispc_cinfo); if (r) goto err_calc_clock_div; sdi->mgr_config.clock_info = dispc_cinfo; pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div; if (pck != vm->pixelclock) { DSSWARN("Could not find exact pixel clock. Requested %lu Hz, got %lu Hz\n", vm->pixelclock, pck); vm->pixelclock = pck; } dss_mgr_set_timings(&sdi->output, vm); r = dss_set_fck_rate(sdi->dss, fck); if (r) goto err_set_dss_clock_div; sdi_config_lcd_manager(sdi); /* * LCLK and PCLK divisors are located in shadow registers, and we * normally write them to DISPC registers when enabling the output. * However, SDI uses pck-free as source clock for its PLL, and pck-free * is affected by the divisors. And as we need the PLL before enabling * the output, we need to write the divisors early. * * It seems just writing to the DISPC register is enough, and we don't * need to care about the shadow register mechanism for pck-free. The * exact reason for this is unknown. */ dispc_mgr_set_clock_div(sdi->dss->dispc, sdi->output.dispc_channel, &sdi->mgr_config.clock_info); dss_sdi_init(sdi->dss, sdi->datapairs); r = dss_sdi_enable(sdi->dss); if (r) goto err_sdi_enable; mdelay(2); r = dss_mgr_enable(&sdi->output); if (r) goto err_mgr_enable; return 0; err_mgr_enable: dss_sdi_disable(sdi->dss); err_sdi_enable: err_set_dss_clock_div: err_calc_clock_div: dispc_runtime_put(sdi->dss->dispc); err_get_dispc: regulator_disable(sdi->vdds_sdi_reg); err_reg_enable: return r; }
static int sdi_display_enable(struct omap_dss_device *dssdev) { struct omap_dss_device *out = &sdi.output; struct omap_video_timings *t = &sdi.timings; unsigned long fck; struct dispc_clock_info dispc_cinfo; unsigned long pck; int r; if (out == NULL || out->manager == NULL) { DSSERR("failed to enable display: no output/manager\n"); return -ENODEV; } r = regulator_enable(sdi.vdds_sdi_reg); if (r) goto err_reg_enable; r = dispc_runtime_get(); if (r) goto err_get_dispc; /* 15.5.9.1.2 */ t->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; t->sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; r = sdi_calc_clock_div(t->pixel_clock * 1000, &fck, &dispc_cinfo); if (r) goto err_calc_clock_div; sdi.mgr_config.clock_info = dispc_cinfo; pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div / 1000; if (pck != t->pixel_clock) { DSSWARN("Could not find exact pixel clock. Requested %d kHz, " "got %lu kHz\n", t->pixel_clock, pck); t->pixel_clock = pck; } dss_mgr_set_timings(out->manager, t); r = dss_set_fck_rate(fck); if (r) goto err_set_dss_clock_div; sdi_config_lcd_manager(dssdev); /* * LCLK and PCLK divisors are located in shadow registers, and we * normally write them to DISPC registers when enabling the output. * However, SDI uses pck-free as source clock for its PLL, and pck-free * is affected by the divisors. And as we need the PLL before enabling * the output, we need to write the divisors early. * * It seems just writing to the DISPC register is enough, and we don't * need to care about the shadow register mechanism for pck-free. The * exact reason for this is unknown. */ dispc_mgr_set_clock_div(out->manager->id, &sdi.mgr_config.clock_info); dss_sdi_init(sdi.datapairs); r = dss_sdi_enable(); if (r) goto err_sdi_enable; mdelay(2); r = dss_mgr_enable(out->manager); if (r) goto err_mgr_enable; return 0; err_mgr_enable: dss_sdi_disable(); err_sdi_enable: err_set_dss_clock_div: err_calc_clock_div: dispc_runtime_put(); err_get_dispc: regulator_disable(sdi.vdds_sdi_reg); err_reg_enable: return r; }