void p8_sbe_init_timer(void) { struct dt_node *np; int64_t rc; uint32_t tick_us; np = dt_find_compatible_node(dt_root, NULL, "ibm,power8-sbe-timer"); if (!np) return; sbe_timer_chip = dt_get_chip_id(np); tick_us = dt_prop_get_u32(np, "tick-time-us"); sbe_timer_inc = usecs_to_tb(tick_us); sbe_timer_target = ~0ull; rc = xscom_read(sbe_timer_chip, 0xE0006, &sbe_last_gen); if (rc) { prerror("SLW: Error %lld reading tmr gen count\n", rc); return; } sbe_last_gen_stamp = mftb(); prlog(PR_INFO, "SLW: Timer facility on chip %d, resolution %dus\n", sbe_timer_chip, tick_us); sbe_has_timer = true; }
static int cfam_hmfsi_probe(struct pdbg_target *target) { struct fsi *fsi = target_to_fsi(target); struct pdbg_target *fsi_parent = target->parent; uint32_t value, port; int rc; /* Enable the port in the upstream control register */ port = dt_prop_get_u32(target, "port"); fsi_read(fsi_parent, 0x3404, &value); value |= 1 << (31 - port); if ((rc = fsi_write(fsi_parent, 0x3404, value))) { PR_ERROR("Unable to enable HMFSI port %d\n", port); return rc; } if ((rc = fsi_read(&fsi->target, 0xc09, &value))) return rc; fsi->chip_type = get_chip_type(value); PR_DEBUG("Found chip type %x\n", fsi->chip_type); if (fsi->chip_type == CHIP_UNKNOWN) return -1; return 0; }