static unsigned
bfin_eppi_io_write_buffer (struct hw *me, const void *source,
int space, address_word addr, unsigned nr_bytes)
{
struct bfin_eppi *eppi = hw_data (me);
bu32 mmr_off;
bu32 value;
bu16 *value16p;
bu32 *value32p;
void *valuep;
if (nr_bytes == 4)
value = dv_load_4 (source);
else
value = dv_load_2 (source);
mmr_off = addr - eppi->base;
valuep = (void *)((unsigned long)eppi + mmr_base() + mmr_off);
value16p = valuep;
value32p = valuep;
HW_TRACE_WRITE ();
switch (mmr_off)
{
case mmr_offset(status):
dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
dv_w1c_2 (value16p, value, 0x1ff);
break;
case mmr_offset(hcount):
case mmr_offset(hdelay):
case mmr_offset(vcount):
case mmr_offset(vdelay):
case mmr_offset(frame):
case mmr_offset(line):
case mmr_offset(clkdiv):
dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
*value16p = value;
break;
case mmr_offset(control):
*value32p = value;
bfin_eppi_gui_setup (eppi);
break;
case mmr_offset(fs1w_hbl):
case mmr_offset(fs1p_avpl):
case mmr_offset(fsw2_lvb):
case mmr_offset(fs2p_lavf):
case mmr_offset(clip):
case mmr_offset(err):
dv_bfin_mmr_require_32 (me, addr, nr_bytes, true);
*value32p = value;
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
break;
}
return nr_bytes;
}
static unsigned
bfin_uart_io_write_buffer (struct hw *me, const void *source,
int space, address_word addr, unsigned nr_bytes)
{
struct bfin_uart *uart = hw_data (me);
bu32 mmr_off;
bu32 value;
bu16 *valuep;
/* Invalid access mode is higher priority than missing register. */
if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
return 0;
value = dv_load_2 (source);
mmr_off = addr - uart->base;
valuep = (void *)((unsigned long)uart + mmr_base() + mmr_off);
HW_TRACE_WRITE ();
/* XXX: All MMRs are "8bit" ... what happens to high 8bits ? */
switch (mmr_off)
{
case mmr_offset(thr):
uart->thr = bfin_uart_write_byte (me, value, uart->mcr);
if (uart->ier & ETBEI)
hw_port_event (me, DV_PORT_TX, 1);
break;
case mmr_offset(ier_set):
uart->ier |= value;
break;
case mmr_offset(ier_clear):
dv_w1c_2 (&uart->ier, value, -1);
break;
case mmr_offset(lsr):
dv_w1c_2 (valuep, value, TFI | BI | FE | PE | OE);
break;
case mmr_offset(rbr):
/* XXX: Writes are ignored ? */
break;
case mmr_offset(msr):
dv_w1c_2 (valuep, value, SCTS);
break;
case mmr_offset(dll):
case mmr_offset(dlh):
case mmr_offset(gctl):
case mmr_offset(lcr):
case mmr_offset(mcr):
case mmr_offset(scr):
*valuep = value;
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
return 0;
}
return nr_bytes;
}
static unsigned
bfin_uart_io_write_buffer (struct hw *me, const void *source,
int space, address_word addr, unsigned nr_bytes)
{
struct bfin_uart *uart = hw_data (me);
bu32 mmr_off;
bu32 value;
bu16 *valuep;
value = dv_load_2 (source);
mmr_off = addr - uart->base;
valuep = (void *)((unsigned long)uart + mmr_base() + mmr_off);
HW_TRACE_WRITE ();
dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
/* XXX: All MMRs are "8bit" ... what happens to high 8bits ? */
switch (mmr_off)
{
case mmr_offset(dll):
if (uart->lcr & DLAB)
uart->dll = value;
else
{
uart->thr = bfin_uart_write_byte (me, value, uart->mcr);
if (uart->ier & ETBEI)
hw_port_event (me, DV_PORT_TX, 1);
}
break;
case mmr_offset(dlh):
if (uart->lcr & DLAB)
uart->dlh = value;
else
{
uart->ier = value;
bfin_uart_reschedule (me);
}
break;
case mmr_offset(iir):
case mmr_offset(lsr):
/* XXX: Writes are ignored ? */
break;
case mmr_offset(lcr):
case mmr_offset(mcr):
case mmr_offset(scr):
case mmr_offset(gctl):
*valuep = value;
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
break;
}
return nr_bytes;
}
static unsigned
bfin_wdog_io_write_buffer (struct hw *me, const void *source,
int space, address_word addr, unsigned nr_bytes)
{
struct bfin_wdog *wdog = hw_data (me);
bu32 mmr_off;
bu32 value;
bu16 *value16p;
bu32 *value32p;
void *valuep;
/* Invalid access mode is higher priority than missing register. */
if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
return 0;
if (nr_bytes == 4)
value = dv_load_4 (source);
else
value = dv_load_2 (source);
mmr_off = addr - wdog->base;
valuep = (void *)((unsigned long)wdog + mmr_base() + mmr_off);
value16p = valuep;
value32p = valuep;
HW_TRACE_WRITE ();
switch (mmr_off)
{
case mmr_offset(ctl):
dv_w1c_2_partial (value16p, value, WDRO);
/* XXX: Should enable an event here to handle timeouts. */
break;
case mmr_offset(cnt):
/* Writes are discarded when enabeld. */
if (!bfin_wdog_enabled (wdog))
{
*value32p = value;
/* Writes to CNT preloads the STAT. */
wdog->stat = wdog->cnt;
}
break;
case mmr_offset(stat):
/* When enabled, writes to STAT reload the counter. */
if (bfin_wdog_enabled (wdog))
wdog->stat = wdog->cnt;
/* XXX: When disabled, are writes just ignored ? */
break;
}
return nr_bytes;
}
static unsigned
bfin_ebiu_sdc_io_write_buffer (struct hw *me, const void *source,
int space, address_word addr, unsigned nr_bytes)
{
struct bfin_ebiu_sdc *sdc = hw_data (me);
bu32 mmr_off;
bu32 value;
bu16 *value16p;
bu32 *value32p;
void *valuep;
if (nr_bytes == 4)
value = dv_load_4 (source);
else
value = dv_load_2 (source);
mmr_off = addr - sdc->base;
valuep = (void *)((unsigned long)sdc + mmr_base() + mmr_off);
value16p = valuep;
value32p = valuep;
HW_TRACE_WRITE ();
switch (mmr_off)
{
case mmr_offset(sdgctl):
/* XXX: SRFS should make external mem unreadable. */
*value32p = value;
break;
case mmr_offset(sdbctl):
if (sdc->type == 561)
{
dv_bfin_mmr_require_32 (me, addr, nr_bytes, true);
*value32p = value;
}
else
{
dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
*value16p = value;
}
break;
case mmr_offset(sdrrc):
dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
*value16p = value;
break;
case mmr_offset(sdstat):
dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
/* XXX: Some bits are W1C ... */
break;
}
return nr_bytes;
}
static unsigned
bfin_gptimer_io_write_buffer (struct hw *me, const void *source, int space,
address_word addr, unsigned nr_bytes)
{
struct bfin_gptimer *gptimer = hw_data (me);
bu32 mmr_off;
bu32 value;
bu16 *value16p;
bu32 *value32p;
void *valuep;
/* Invalid access mode is higher priority than missing register. */
if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
return 0;
if (nr_bytes == 4)
value = dv_load_4 (source);
else
value = dv_load_2 (source);
mmr_off = addr - gptimer->base;
valuep = (void *)((unsigned long)gptimer + mmr_base() + mmr_off);
value16p = valuep;
value32p = valuep;
HW_TRACE_WRITE ();
switch (mmr_off)
{
case mmr_offset(config):
if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
return 0;
*value16p = value;
break;
case mmr_offset(counter):
case mmr_offset(period):
case mmr_offset(width):
if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
return 0;
*value32p = value;
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
return 0;
}
return nr_bytes;
}
static unsigned
bfin_spi_io_write_buffer (struct hw *me, const void *source, int space,
address_word addr, unsigned nr_bytes)
{
struct bfin_spi *spi = hw_data (me);
bu32 mmr_off;
bu32 value;
bu16 *valuep;
/* Invalid access mode is higher priority than missing register. */
if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
return 0;
value = dv_load_2 (source);
mmr_off = addr - spi->base;
valuep = (void *)((unsigned long)spi + mmr_base() + mmr_off);
HW_TRACE_WRITE ();
switch (mmr_off)
{
case mmr_offset(stat):
dv_w1c_2 (valuep, value, ~(SPIF | TXS | RXS));
break;
case mmr_offset(tdbr):
*valuep = value;
if (bfin_spi_enabled (spi) && bfin_spi_timod (spi) == TDBR_CORE)
{
spi->stat |= RXS;
spi->stat &= ~TXS;
}
break;
case mmr_offset(rdbr):
case mmr_offset(ctl):
case mmr_offset(flg):
case mmr_offset(baud):
case mmr_offset(shadow):
*valuep = value;
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
return 0;
}
return nr_bytes;
}
static unsigned
bfin_ebiu_ddrc_io_write_buffer (struct hw *me, const void *source,
int space, address_word addr, unsigned nr_bytes)
{
struct bfin_ebiu_ddrc *ddrc = hw_data (me);
bu32 mmr_off;
bu32 value;
bu16 *value16p;
bu32 *value32p;
void *valuep;
/* Invalid access mode is higher priority than missing register. */
if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
return 0;
if (nr_bytes == 4)
value = dv_load_4 (source);
else
value = dv_load_2 (source);
mmr_off = addr - ddrc->base;
valuep = (void *)((unsigned long)ddrc + mmr_base() + mmr_off);
value16p = valuep;
value32p = valuep;
HW_TRACE_WRITE ();
switch (mmr_off)
{
case mmr_offset(errmst):
case mmr_offset(rstctl):
if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
return 0;
*value16p = value;
break;
default:
if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
return 0;
*value32p = value;
break;
}
return nr_bytes;
}
static unsigned
bfin_rtc_io_write_buffer (struct hw *me, const void *source,
int space, address_word addr, unsigned nr_bytes)
{
struct bfin_rtc *rtc = hw_data (me);
bu32 mmr_off;
bu32 value;
bu16 *value16p;
bu32 *value32p;
void *valuep;
if (nr_bytes == 4)
value = dv_load_4 (source);
else
value = dv_load_2 (source);
mmr_off = addr - rtc->base;
valuep = (void *)((unsigned long)rtc + mmr_base() + mmr_off);
value16p = valuep;
value32p = valuep;
HW_TRACE_WRITE ();
/* XXX: These probably need more work. */
switch (mmr_off)
{
case mmr_offset(stat):
/* XXX: Ignore these since we are wired to host. */
break;
case mmr_offset(istat):
dv_w1c_2 (value16p, value, ~(1 << 14));
break;
case mmr_offset(alarm):
break;
case mmr_offset(ictl):
/* XXX: This should schedule an event handler. */
case mmr_offset(swcnt):
case mmr_offset(pren):
break;
}
return nr_bytes;
}
static unsigned
bfin_ppi_io_write_buffer (struct hw *me, const void *source, int space,
address_word addr, unsigned nr_bytes)
{
struct bfin_ppi *ppi = hw_data (me);
bu32 mmr_off;
bu32 value;
bu16 *valuep;
value = dv_load_2 (source);
mmr_off = addr - ppi->base;
valuep = (void *)((unsigned long)ppi + mmr_base() + mmr_off);
HW_TRACE_WRITE ();
dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
switch (mmr_off)
{
case mmr_offset(control):
*valuep = value;
bfin_ppi_gui_setup (ppi);
break;
case mmr_offset(count):
case mmr_offset(delay):
case mmr_offset(frame):
*valuep = value;
break;
case mmr_offset(status):
dv_w1c_2 (valuep, value, ~(1 << 10));
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
break;
}
return nr_bytes;
}
static unsigned
bfin_gpio_io_write_buffer (struct hw *me, const void *source, int space,
address_word addr, unsigned nr_bytes)
{
struct bfin_gpio *port = hw_data (me);
bu32 mmr_off;
bu32 value;
bu16 *value16p;
bu32 *value32p;
void *valuep;
mmr_off = addr - port->base;
/* Invalid access mode is higher priority than missing register. */
if (mmr_off == mmr_offset (mux))
{
if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
return 0;
}
else
if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
return 0;
if (nr_bytes == 4)
value = dv_load_4 (source);
else
value = dv_load_2 (source);
valuep = (void *)((unsigned long)port + mmr_base() + mmr_off);
value16p = valuep;
value32p = valuep;
HW_TRACE_WRITE ();
switch (mmr_off)
{
case mmr_offset(fer):
case mmr_offset(data):
case mmr_offset(inen):
*value16p = value;
break;
case mmr_offset(clear):
/* We want to clear the related data MMR. */
dv_w1c_2 (&port->data, value, -1);
break;
case mmr_offset(set):
/* We want to set the related data MMR. */
port->data |= value;
break;
case mmr_offset(dir_clear):
dv_w1c_2 (&port->dir, value, -1);
break;
case mmr_offset(dir_set):
port->dir |= value;
break;
case mmr_offset(mux):
*value32p = value;
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
return 0;
}
/* If tweaking output pins, make sure we send updated port info. */
switch (mmr_off)
{
case mmr_offset(data):
case mmr_offset(set):
case mmr_offset(clear):
case mmr_offset(dir_set):
{
int i;
bu32 bit;
for (i = 0; i < 16; ++i)
{
bit = (1 << i);
if (!(port->inen & bit))
hw_port_event (me, i, !!(port->data & bit));
}
break;
}
}
return nr_bytes;
}