static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie) { struct pcie_port *pp = &spear13xx_pcie->pp; struct pcie_app_reg *app_reg = spear13xx_pcie->app_base; u32 val; u32 exp_cap_off = EXP_CAP_ID_OFFSET; if (dw_pcie_link_up(pp)) { dev_err(pp->dev, "link already up\n"); return 0; } dw_pcie_setup_rc(pp); /* * this controller support only 128 bytes read size, however its * default value in capability register is 512 bytes. So force * it to 128 here. */ dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val); val &= ~PCI_EXP_DEVCTL_READRQ; dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val); dw_pcie_cfg_write(pp->dbi_base + PCI_VENDOR_ID, 2, 0x104A); dw_pcie_cfg_write(pp->dbi_base + PCI_DEVICE_ID, 2, 0xCD80); /* * if is_gen1 is set then handle it, so that some buggy card * also works */ if (spear13xx_pcie->is_gen1) { dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP, 4, &val); if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { val &= ~((u32)PCI_EXP_LNKCAP_SLS); val |= PCI_EXP_LNKCAP_SLS_2_5GB; dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP, 4, val); } dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2, 2, &val); if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { val &= ~((u32)PCI_EXP_LNKCAP_SLS); val |= PCI_EXP_LNKCAP_SLS_2_5GB; dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2, 2, val); } } /* enable ltssm */ writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID) | (1 << APP_LTSSM_ENABLE_ID) | ((u32)1 << REG_TRANSLATION_ENABLE), &app_reg->app_ctrl_0); return dw_pcie_wait_for_link(pp); }
static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, u32 val) { int ret; exynos_pcie_sideband_dbi_w_mode(pp, true); ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where, size, val); exynos_pcie_sideband_dbi_w_mode(pp, false); return ret; }
static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, u32 val) { struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); int ret; exynos_pcie_sideband_dbi_w_mode(exynos_pcie, true); ret = dw_pcie_cfg_write(pp->dbi_base + where, size, val); exynos_pcie_sideband_dbi_w_mode(exynos_pcie, false); return ret; }
int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) { struct keystone_pcie *ks_pcie = to_keystone_pcie(pp); u8 bus_num = bus->number; void __iomem *addr; addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn); return dw_pcie_cfg_write(addr + (where & ~0x3), where, size, val); }