static void dwc3_ep0_xfernotready(struct dwc3 *dwc, const struct dwc3_event_depevt *event) { u8 epnum; int ret; dwc->setup_packet_pending = true; epnum = event->endpoint_number; switch (event->status) { case DEPEVT_STATUS_CONTROL_DATA: dev_vdbg(dwc->dev, "Control Data\n"); /* * We already have a DATA transfer in the controller's cache, * if we receive a XferNotReady(DATA) we will ignore it, unless * it's for the wrong direction. * * In that case, we must issue END_TRANSFER command to the Data * Phase we already have started and issue SetStall on the * control endpoint. */ if (dwc->ep0_expect_in != event->endpoint_number) { struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in]; dev_vdbg(dwc->dev, "Wrong direction for Data phase\n"); dwc3_ep0_end_control_data(dwc, dep); dbg_event(epnum, "WRONGDR", 0); dwc3_ep0_stall_and_restart(dwc); return; } if (zlp_required) { zlp_required = false; ret = dwc3_ep0_start_trans(dwc, epnum, dwc->ctrl_req_addr, 0, DWC3_TRBCTL_CONTROL_DATA); dbg_event(epnum, "ZLP", ret); WARN_ON(ret < 0); } break; case DEPEVT_STATUS_CONTROL_STATUS: if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) return; dev_vdbg(dwc->dev, "Control Status\n"); zlp_required = false; dwc->ep0state = EP0_STATUS_PHASE; if (dwc->delayed_status && list_empty(&dwc->eps[0]->request_list)) { WARN_ON_ONCE(event->endpoint_number != 1); dev_vdbg(dwc->dev, "Mass Storage delayed status\n"); return; } dwc->delayed_status = false; dwc3_ep0_do_control_status(dwc, event); } }
static void dwc3_ep0_xfernotready(struct dwc3 *dwc, const struct dwc3_event_depevt *event) { dwc->setup_packet_pending = true; switch (event->status) { case DEPEVT_STATUS_CONTROL_DATA: dev_vdbg(dwc->dev, "Control Data\n"); /* * We already have a DATA transfer in the controller's cache, * if we receive a XferNotReady(DATA) we will ignore it, unless * it's for the wrong direction. * * In that case, we must issue END_TRANSFER command to the Data * Phase we already have started and issue SetStall on the * control endpoint. */ if (dwc->ep0_expect_in != event->endpoint_number) { struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in]; dev_vdbg(dwc->dev, "Wrong direction for Data phase\n"); dwc3_ep0_end_control_data(dwc, dep); dwc3_ep0_stall_and_restart(dwc); return; } /* * Per databook, if an XferNotready(Data) is received after * XferComplete(Data), one possible reason is host is trying * to complete data stage by moving a 0-length packet. * * REVISIT in case of other cases */ if (dwc->ep0_next_event == DWC3_EP0_NRDY_STATUS) { u32 size = 0; struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; if (dep->number == 0) size = dep->endpoint.maxpacket; dwc3_ep0_start_trans(dwc, dep->number, dwc->ctrl_req_addr, size, DWC3_TRBCTL_CONTROL_DATA); } break; case DEPEVT_STATUS_CONTROL_STATUS: if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) return; dev_vdbg(dwc->dev, "Control Status\n"); dwc->ep0state = EP0_STATUS_PHASE; if (dwc->delayed_status) { WARN_ON_ONCE(event->endpoint_number != 1); dev_vdbg(dwc->dev, "Mass Storage delayed status\n"); if (list_empty(&dwc->eps[0]->request_list)) return; else dwc->delayed_status = false; } dwc3_ep0_do_control_status(dwc, event); } }