static void amd8131_pcix_exit(struct amd8131_dev_info *dev_info) { u32 val32; struct pci_dev *dev = dev_info->dev; edac_pci_read_dword(dev, REG_INT_CTLR, &val32); val32 &= ~(INT_CTLR_PERR | INT_CTLR_SERR | INT_CTLR_DTSE); edac_pci_write_dword(dev, REG_INT_CTLR, val32); edac_pci_read_dword(dev, REG_STS_CMD, &val32); val32 &= ~STS_CMD_SERREN; edac_pci_write_dword(dev, REG_STS_CMD, val32); edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32); val32 &= ~LNK_CTRL_CRCFEN; edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32); edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32); val32 &= ~LNK_CTRL_CRCFEN; edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32); }
static void amd8111_pci_bridge_exit(struct amd8111_pci_info *pci_info) { u32 val32; struct pci_dev *dev = pci_info->dev; if (edac_op_state == EDAC_OPSTATE_POLL) { /* Disable System Error reporting */ edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32); val32 &= ~PCI_STSCMD_SERREN; edac_pci_write_dword(dev, REG_PCI_STSCMD, val32); /* Disable CRC flood packets */ edac_pci_read_dword(dev, REG_HT_LINK, &val32); val32 &= ~HT_LINK_CRCFEN; edac_pci_write_dword(dev, REG_HT_LINK, val32); edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32); val32 &= ~PCI_INTBRG_CTRL_POLL_MASK; edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32); } }
static void amd8131_pcix_init(struct amd8131_dev_info *dev_info) { u32 val32; struct pci_dev *dev = dev_info->dev; /* First clear error detection flags */ edac_pci_read_dword(dev, REG_MEM_LIM, &val32); if (val32 & MEM_LIMIT_MASK) edac_pci_write_dword(dev, REG_MEM_LIM, val32); /* Clear Discard Timer Timedout flag */ edac_pci_read_dword(dev, REG_INT_CTLR, &val32); if (val32 & INT_CTLR_DTS) edac_pci_write_dword(dev, REG_INT_CTLR, val32); /* Clear CRC Error flag on link side A */ edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32); if (val32 & LNK_CTRL_CRCERR_A) edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32); /* Clear CRC Error flag on link side B */ edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32); if (val32 & LNK_CTRL_CRCERR_B) edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32); /* * Then enable all error detections. * * Setup Discard Timer Sync Flood Enable, * System Error Enable and Parity Error Enable. */ edac_pci_read_dword(dev, REG_INT_CTLR, &val32); val32 |= INT_CTLR_PERR | INT_CTLR_SERR | INT_CTLR_DTSE; edac_pci_write_dword(dev, REG_INT_CTLR, val32); /* Enable overall SERR Error detection */ edac_pci_read_dword(dev, REG_STS_CMD, &val32); val32 |= STS_CMD_SERREN; edac_pci_write_dword(dev, REG_STS_CMD, val32); /* Setup CRC Flood Enable for link side A */ edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32); val32 |= LNK_CTRL_CRCFEN; edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32); /* Setup CRC Flood Enable for link side B */ edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32); val32 |= LNK_CTRL_CRCFEN; edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32); }
static void amd8131_pcix_exit(struct amd8131_dev_info *dev_info) { u32 val32; struct pci_dev *dev = dev_info->dev; edac_pci_read_dword(dev, REG_INT_CTLR, &val32); val32 &= ~(INT_CTLR_PERR | INT_CTLR_SERR | INT_CTLR_DTSE); edac_pci_write_dword(dev, REG_INT_CTLR, val32); /* Disable overall System Error detection */ edac_pci_read_dword(dev, REG_STS_CMD, &val32); val32 &= ~STS_CMD_SERREN; edac_pci_write_dword(dev, REG_STS_CMD, val32); /* Disable CRC Sync Flood on link side A */ edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32); val32 &= ~LNK_CTRL_CRCFEN; edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32); /* Disable CRC Sync Flood on link side B */ edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32); val32 &= ~LNK_CTRL_CRCFEN; edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32); }
static void amd8131_pcix_init(struct amd8131_dev_info *dev_info) { u32 val32; struct pci_dev *dev = dev_info->dev; edac_pci_read_dword(dev, REG_MEM_LIM, &val32); if (val32 & MEM_LIMIT_MASK) edac_pci_write_dword(dev, REG_MEM_LIM, val32); edac_pci_read_dword(dev, REG_INT_CTLR, &val32); if (val32 & INT_CTLR_DTS) edac_pci_write_dword(dev, REG_INT_CTLR, val32); edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32); if (val32 & LNK_CTRL_CRCERR_A) edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32); edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32); if (val32 & LNK_CTRL_CRCERR_B) edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32); edac_pci_read_dword(dev, REG_INT_CTLR, &val32); val32 |= INT_CTLR_PERR | INT_CTLR_SERR | INT_CTLR_DTSE; edac_pci_write_dword(dev, REG_INT_CTLR, val32); edac_pci_read_dword(dev, REG_STS_CMD, &val32); val32 |= STS_CMD_SERREN; edac_pci_write_dword(dev, REG_STS_CMD, val32); edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32); val32 |= LNK_CTRL_CRCFEN; edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32); edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32); val32 |= LNK_CTRL_CRCFEN; edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32); }
/* * device-specific methods for amd8111 PCI Bridge Controller * * Error Reporting and Handling for amd8111 chipset could be found * in its datasheet 3.1.2 section, P37 */ static void amd8111_pci_bridge_init(struct amd8111_pci_info *pci_info) { u32 val32; struct pci_dev *dev = pci_info->dev; /* First clear error detection flags on the host interface */ /* Clear SSE/SMA/STA flags in the global status register*/ edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32); if (val32 & PCI_STSCMD_CLEAR_MASK) edac_pci_write_dword(dev, REG_PCI_STSCMD, val32); /* Clear CRC and Link Fail flags in HT Link Control reg */ edac_pci_read_dword(dev, REG_HT_LINK, &val32); if (val32 & HT_LINK_CLEAR_MASK) edac_pci_write_dword(dev, REG_HT_LINK, val32); /* Second clear all fault on the secondary interface */ /* Clear error flags in the memory-base limit reg. */ edac_pci_read_dword(dev, REG_MEM_LIM, &val32); if (val32 & MEM_LIMIT_CLEAR_MASK) edac_pci_write_dword(dev, REG_MEM_LIM, val32); /* Clear Discard Timer Expired flag in Interrupt/Bridge Control reg */ edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32); if (val32 & PCI_INTBRG_CTRL_CLEAR_MASK) edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32); /* Last enable error detections */ if (edac_op_state == EDAC_OPSTATE_POLL) { /* Enable System Error reporting in global status register */ edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32); val32 |= PCI_STSCMD_SERREN; edac_pci_write_dword(dev, REG_PCI_STSCMD, val32); /* Enable CRC Sync flood packets to HyperTransport Link */ edac_pci_read_dword(dev, REG_HT_LINK, &val32); val32 |= HT_LINK_CRCFEN; edac_pci_write_dword(dev, REG_HT_LINK, val32); /* Enable SSE reporting etc in Interrupt control reg */ edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32); val32 |= PCI_INTBRG_CTRL_POLL_MASK; edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32); } }
static void amd8131_pcix_check(struct edac_pci_ctl_info *edac_dev) { struct amd8131_dev_info *dev_info = edac_dev->pvt_info; struct pci_dev *dev = dev_info->dev; u32 val32; edac_pci_read_dword(dev, REG_MEM_LIM, &val32); if (val32 & MEM_LIMIT_MASK) { printk(KERN_INFO "Error(s) in mem limit register " "on %s bridge\n", dev_info->ctl_name); printk(KERN_INFO "DPE: %d, RSE: %d, RMA: %d\n" "RTA: %d, STA: %d, MDPE: %d\n", val32 & MEM_LIMIT_DPE, val32 & MEM_LIMIT_RSE, val32 & MEM_LIMIT_RMA, val32 & MEM_LIMIT_RTA, val32 & MEM_LIMIT_STA, val32 & MEM_LIMIT_MDPE); val32 |= MEM_LIMIT_MASK; edac_pci_write_dword(dev, REG_MEM_LIM, val32); edac_pci_handle_npe(edac_dev, edac_dev->ctl_name); } edac_pci_read_dword(dev, REG_INT_CTLR, &val32); if (val32 & INT_CTLR_DTS) { printk(KERN_INFO "Error(s) in interrupt and control register " "on %s bridge\n", dev_info->ctl_name); printk(KERN_INFO "DTS: %d\n", val32 & INT_CTLR_DTS); val32 |= INT_CTLR_DTS; edac_pci_write_dword(dev, REG_INT_CTLR, val32); edac_pci_handle_npe(edac_dev, edac_dev->ctl_name); } edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32); if (val32 & LNK_CTRL_CRCERR_A) { printk(KERN_INFO "Error(s) in link conf and control register " "on %s bridge\n", dev_info->ctl_name); printk(KERN_INFO "CRCERR: %d\n", val32 & LNK_CTRL_CRCERR_A); val32 |= LNK_CTRL_CRCERR_A; edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32); edac_pci_handle_npe(edac_dev, edac_dev->ctl_name); } edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32); if (val32 & LNK_CTRL_CRCERR_B) { printk(KERN_INFO "Error(s) in link conf and control register " "on %s bridge\n", dev_info->ctl_name); printk(KERN_INFO "CRCERR: %d\n", val32 & LNK_CTRL_CRCERR_B); val32 |= LNK_CTRL_CRCERR_B; edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32); edac_pci_handle_npe(edac_dev, edac_dev->ctl_name); } }
static void amd8111_pci_bridge_check(struct edac_pci_ctl_info *edac_dev) { struct amd8111_pci_info *pci_info = edac_dev->pvt_info; struct pci_dev *dev = pci_info->dev; u32 val32; /* Check out PCI Bridge Status and Command Register */ edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32); if (val32 & PCI_STSCMD_CLEAR_MASK) { printk(KERN_INFO "Error(s) in PCI bridge status and command" "register on device %s\n", pci_info->ctl_name); printk(KERN_INFO "SSE: %d, RMA: %d, RTA: %d\n", (val32 & PCI_STSCMD_SSE) != 0, (val32 & PCI_STSCMD_RMA) != 0, (val32 & PCI_STSCMD_RTA) != 0); val32 |= PCI_STSCMD_CLEAR_MASK; edac_pci_write_dword(dev, REG_PCI_STSCMD, val32); edac_pci_handle_npe(edac_dev, edac_dev->ctl_name); } /* Check out HyperTransport Link Control Register */ edac_pci_read_dword(dev, REG_HT_LINK, &val32); if (val32 & HT_LINK_LKFAIL) { printk(KERN_INFO "Error(s) in hypertransport link control" "register on device %s\n", pci_info->ctl_name); printk(KERN_INFO "LKFAIL: %d\n", (val32 & HT_LINK_LKFAIL) != 0); val32 |= HT_LINK_LKFAIL; edac_pci_write_dword(dev, REG_HT_LINK, val32); edac_pci_handle_npe(edac_dev, edac_dev->ctl_name); } /* Check out PCI Interrupt and Bridge Control Register */ edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32); if (val32 & PCI_INTBRG_CTRL_DTSTAT) { printk(KERN_INFO "Error(s) in PCI interrupt and bridge control" "register on device %s\n", pci_info->ctl_name); printk(KERN_INFO "DTSTAT: %d\n", (val32 & PCI_INTBRG_CTRL_DTSTAT) != 0); val32 |= PCI_INTBRG_CTRL_DTSTAT; edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32); edac_pci_handle_npe(edac_dev, edac_dev->ctl_name); } /* Check out PCI Bridge Memory Base-Limit Register */ edac_pci_read_dword(dev, REG_MEM_LIM, &val32); if (val32 & MEM_LIMIT_CLEAR_MASK) { printk(KERN_INFO "Error(s) in mem limit register on %s device\n", pci_info->ctl_name); printk(KERN_INFO "DPE: %d, RSE: %d, RMA: %d\n" "RTA: %d, STA: %d, MDPE: %d\n", (val32 & MEM_LIMIT_DPE) != 0, (val32 & MEM_LIMIT_RSE) != 0, (val32 & MEM_LIMIT_RMA) != 0, (val32 & MEM_LIMIT_RTA) != 0, (val32 & MEM_LIMIT_STA) != 0, (val32 & MEM_LIMIT_MDPE) != 0); val32 |= MEM_LIMIT_CLEAR_MASK; edac_pci_write_dword(dev, REG_MEM_LIM, val32); edac_pci_handle_npe(edac_dev, edac_dev->ctl_name); } }