/**
* @brief Low level HAL driver initialization.
*
* @notapi
*/
void hal_lld_init(void) {
uint32_t reg;
/* The system is switched to the RUN0 mode, the default for normal
operations.*/
if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == OSAL_FAILED) {
SPC5_CLOCK_FAILURE_HOOK();
}
/* INTC initialization, software vector mode, 4 bytes vectors, starting
at priority 0.*/
INTC.MCR.R = 0;
INTC.CPR.R = 0;
INTC.IACKR.R = (uint32_t)_vectors;
/* PIT channel 0 initialization for Kernel ticks, the PIT is configured
to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other
modes.*/
INTC.PSR[59].R = SPC5_PIT0_IRQ_PRIORITY;
halSPCSetPeripheralClockMode(92,
SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
reg = halSPCGetSystemClock() / OSAL_ST_FREQUENCY - 1;
PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */
PIT.CH[0].LDVAL.R = reg;
PIT.CH[0].CVAL.R = reg;
PIT.CH[0].TFLG.R = 1; /* Interrupt flag cleared. */
PIT.CH[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */
/* EDMA initialization.*/
edmaInit();
}
void main(void) {
Uint32 timestamp, delta;
timestamp = Timestamp_get32();
EDMA3_DRV_Result edmaResult = EDMA3_DRV_SOK;
unsigned const short *L1d_p9;
unsigned const short *L1d_p10;
unsigned short *mainSourceImg;
unsigned short *referenceImg1;
L1d_p9 = (unsigned const short *) Memory_alloc((IHeap_Handle) l2Heap, (NUM_BYTES1), 0, NULL);
L1d_p10 = (unsigned const short *) Memory_alloc((IHeap_Handle) l2Heap, (NUM_BYTES3), 0, NULL);
referenceImg1 = (unsigned short *) Memory_alloc((IHeap_Handle) l2Heap, (NUM_BYTES1), 0, NULL);
mainSourceImg = (unsigned short *) Memory_alloc((IHeap_Handle) l2Heap, (NUM_BYTES3), 0, NULL);
int i;
edmaWait4Completion(1);
for (i = 0; i < 1024; i++) {
mainSourceImg[i] = 1;
}
edmaInit();
edmaInitiateXfer(L1d_p10, mainSourceImg, NUM_BYTES2, 8, 1, NUM_BYTES2, NUM_BYTES2, 1, 1, 0, 1);
edmaWait4Completion(0);
edmaInitiateXfer(L1d_p9, referenceImg1, NUM_BYTES2, 2, 1, NUM_BYTES2, NUM_BYTES2, 1, 1, 0, 1);
edmaWait4Completion(0);
delta = Timestamp_get32()-timestamp;
}
