static int tegra_ehci_bus_resume(struct usb_hcd *hcd)
{
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
struct tegra_hcd_platform_data *pdata;
/* initialize the platform data pointer */
pdata = hcd->self.controller->platform_data;
#ifdef CONFIG_USB_OTG_UTILS
if (pdata->otg_mode && ehci->transceiver) {
if (ehci->transceiver->state != OTG_STATE_A_HOST) {
/* we are not in host mode, return */
return 0;
}
}
#endif
if (!pdata->otg_mode && pdata->id_detect==ID_PIN_CABLE_ID) {
u32 status;
/* read ID pin status */
status = readl(hcd->regs + TEGRA_USB_PHY_WAKEUP_REG_OFFSET);
/* If Id pin is high no host then return */
if (status & TEGRA_USB_ID_PIN_STATUS) {
return 0;
}
}
//if (!ehci->host_resumed) {
// tegra_ehci_power_up(hcd);
//}
return ehci_bus_resume(hcd);
}
int s5p_ehci_bus_resume(struct usb_hcd *hcd)
{
/* When suspend is failed, re-enable clocks & PHY */
pm_runtime_resume(hcd->self.controller);
return ehci_bus_resume(hcd);
}
static int ehci_fsl_bus_resume(struct usb_hcd *hcd)
{
int ret = 0;
struct fsl_usb2_platform_data *pdata;
pdata = hcd->self.controller->platform_data;
printk(KERN_DEBUG "%s, %s\n", __func__, pdata->name);
/*
* At otg mode, it should not call host resume for usb gadget device
* Otherwise, this usb device can't be recognized as a gadget
*/
if (hcd->self.is_b_host) {
return -ESHUTDOWN;
}
if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
fsl_usb_clk_gate(hcd->self.controller->platform_data, true);
usb_host_set_wakeup(hcd->self.controller, false);
fsl_usb_lowpower_mode(pdata, false);
}
if (pdata->platform_resume)
pdata->platform_resume(pdata);
ret = ehci_bus_resume(hcd);
if (ret)
return ret;
return ret;
}
static int ehci_brcm_resume(struct usb_hcd *hcd)
{
int ret = 0;
brcm_usb_resume(hcd);
if (brcm_pm_deep_sleep()) {
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
usb_root_hub_lost_power(hcd->self.root_hub);
/*
* SWLINUX-1705: Avoid OUT packet underflows during high memory
* bus usage
* port_status[0x0f] = Broadcom-proprietary USB_EHCI_INSNREG00
* @ 0x90
*/
ehci_writel(ehci, 0x00800040, &ehci->regs->port_status[0x10]);
ehci_writel(ehci, 0x00000001, &ehci->regs->port_status[0x12]);
(void)ehci_halt(ehci);
(void)ehci_reset(ehci);
ehci_writel(ehci, ehci->command, &ehci->regs->command);
ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
/* unblock posted writes */
ehci_readl(ehci, &ehci->regs->command);
ehci_writel(ehci, 0, &ehci->regs->intr_enable);
/* re-init operational registers */
ehci_writel(ehci, 0, &ehci->regs->segment);
ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
ehci_writel(ehci, (u32) ehci->async->qh_dma,
&ehci->regs->async_next);
/* restore CMD_RUN, framelist size, and irq threshold */
ehci_writel(ehci, ehci->command, &ehci->regs->command);
/* Some controller/firmware combinations need a delay during
* which they set up the port statuses. See Bugzilla #8190. */
/* SWLINUX-1929 need extra delay here */
msleep(10);
ehci->next_statechange = jiffies + msecs_to_jiffies(5);
hcd->state = HC_STATE_RUNNING;
/* Now we can safely re-enable irqs */
ehci_writel(ehci, INTR_MASK, &ehci->regs->intr_enable);
/* here we "know" root ports should always stay powered */
ehci_port_power(ehci, 1);
return 0;
}
ehci_prepare_ports_for_controller_resume(hcd_to_ehci(hcd));
ret = ehci_bus_resume(hcd);
return ret;
}
static int ehci_omap_bus_resume(struct usb_hcd *hcd)
{
int ret;
printk(KERN_DEBUG " omap_bus_resume\n");
ret = ehci_bus_resume(hcd);
return ret;
}
static int usb_ehci_bus_resume(struct usb_hcd *hcd)
{
int ret = 0;
omap_ehci_bus_resume(gb_omap->dev);
ret = ehci_bus_resume(hcd);
return ret;
}
static int tegra_ehci_bus_resume(struct usb_hcd *hcd)
{
struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
if (tegra->bus_suspended && tegra->power_down_on_bus_suspend) {
tegra_usb_resume(hcd);
tegra->bus_suspended = 0;
}
return ehci_bus_resume(hcd);
}
static int ehci_msm_bus_resume(struct usb_hcd *hcd)
{
struct msmusb_hcd *mhcd = hcd_to_mhcd(hcd);
usb_lpm_exit(hcd);
if (cancel_work_sync(&(mhcd->lpm_exit_work)))
usb_lpm_exit_w(&mhcd->lpm_exit_work);
return ehci_bus_resume(hcd);
}
static int tegra_ehci_bus_resume(struct usb_hcd *hcd)
{
struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
int err = 0;
EHCI_DBG("%s() BEGIN\n", __func__);
mutex_lock(&tegra->sync_lock);
usb_phy_set_suspend(get_usb_phy(tegra->phy), 0);
err = ehci_bus_resume(hcd);
mutex_unlock(&tegra->sync_lock);
EHCI_DBG("%s() END\n", __func__);
return err;
}
static int ehci_omap_bus_resume(struct usb_hcd *hcd)
{
struct ehci_hcd_omap *omap = platform_get_drvdata(to_platform_device(hcd->self.controller));
struct ehci_hcd *ehci = omap->ehci;
struct usb_bus *bus = hcd_to_bus(hcd);
int ret;
#ifdef CONFIG_LOGIC_OMAP3530_USB3320_HACK
/* Remove the GPIO hack; this allows the controller to talk to the PHY again */
usb3320_hack_remove();
#endif // CONFIG_LOGIC_OMAP3530_USB3320_HACK
ehci_omap_dev_resume(bus->controller);
omap_init_uhh_registers(omap, hcd);
/* Initial setup code from the EHCI driver */
ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
ehci->command |= CMD_RUN;
ehci_writel(ehci, ehci->command, &ehci->regs->command);
dbg_cmd (ehci, "init", ehci->command);
ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
/* Give it time to sink in */
msleep(5);
/* reset the USB PHY */
if (omap->phy_reset)
ehci_omap_phy_reset(omap);
ehci_writel(omap->ehci, CMD_RUN, &omap->ehci->regs->command);
msleep(1);
ehci_port_power(ehci, 1);
msleep(1);
ret = ehci_bus_resume(hcd);
return ret;
}
static int ehci_omap_bus_resume(struct usb_hcd *hcd)
{
struct device *dev = hcd->self.controller;
struct uhhtll_apis *uhhtllp = dev->platform_data;
int ret = 0;
if (uhhtllp && uhhtllp->resume)
ret = uhhtllp->resume(OMAP_EHCI);
if (!ret)
ret = ehci_bus_resume(hcd);
return ret;
}
static int ehci_omap_bus_resume(struct usb_hcd *hcd)
{
u32 sysconfig;
unsigned long flags;
struct ehci_hcd_omap *omap = dev_get_drvdata(hcd->self.controller);
dev_dbg(hcd->self.controller, "%s %ld %lu\n", __func__,
in_interrupt(), jiffies);
#ifdef CONFIG_HAS_WAKELOCK
wake_lock(&omap->ehci->wake_lock_ehci_pm);
#endif
spin_lock_irqsave(&usb_clocks_lock, flags);
if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
if (omap->usbtll_fck)
clk_enable(omap->usbtll_fck);
mdelay(1);
ehci_omap_writel(omap->tll_base, OMAP_USBTLL_IRQENABLE, 0);
ehci_omap_writel(omap->tll_base, OMAP_USBTLL_IRQSTATUS, 7);
ehci_omap_writel(omap->tll_base, OMAP_TLL_SHARED_CONF,
1 | ehci_omap_readl(omap->tll_base,
OMAP_TLL_SHARED_CONF));
if (omap->usbhost2_120m_fck)
clk_enable(omap->usbhost2_120m_fck);
if (omap->usbhost1_48m_fck)
clk_enable(omap->usbhost1_48m_fck);
/* Put UHH in NoStandby mode */
sysconfig = ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG);
sysconfig &= ~OMAP_UHH_SYSCONFIG_MIDLEMODE_MASK;
sysconfig |= OMAP_UHH_SYSCONFIG_NOSTBYMODE;
ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, sysconfig);
/* Put UHH in NoIdle mode */
sysconfig = ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG);
sysconfig &= ~OMAP_UHH_SYSCONFIG_SIDLEMODE_MASK;
sysconfig |= OMAP_UHH_SYSCONFIG_NOIDLEMODE;
ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, sysconfig);
sysconfig = ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG);
set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
enable_irq(hcd->irq);
}
spin_unlock_irqrestore(&usb_clocks_lock, flags);
return ehci_bus_resume(hcd);
}
static int ehci_msm_bus_resume(struct usb_hcd *hcd)
{
struct msmusb_hcd *mhcd = hcd_to_mhcd(hcd);
wake_lock(&mhcd->wlock);
if (PHY_TYPE(mhcd->pdata->phy_info) == USB_PHY_INTEGRATED) {
otg_set_suspend(mhcd->xceiv, 0);
} else {
usb_lpm_exit(hcd);
if (cancel_work_sync(&(mhcd->lpm_exit_work)))
usb_lpm_exit_w(&mhcd->lpm_exit_work);
}
return ehci_bus_resume(hcd);
}
static int ehci_msm_bus_resume(struct usb_hcd *hcd)
{
struct msmusb_hcd *mhcd = hcd_to_mhcd(hcd);
struct device *dev = hcd->self.controller;
wake_lock(&mhcd->wlock);
pm_runtime_get_noresume(dev);
pm_runtime_resume(dev);
if (PHY_TYPE(mhcd->pdata->phy_info) == USB_PHY_INTEGRATED) {
usb_phy_set_suspend(mhcd->xceiv, 0);
} else { /* PMIC serial phy */
usb_lpm_exit(hcd);
if (cancel_work_sync(&(mhcd->lpm_exit_work)))
usb_lpm_exit_w(&mhcd->lpm_exit_work);
}
return ehci_bus_resume(hcd);
}
static int tegra_ehci_bus_resume(struct usb_hcd *hcd)
{
struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
int err = 0;
EHCI_DBG("%s() BEGIN\n", __func__);
#ifdef CONFIG_TEGRA_EHCI_BOOST_CPU_FREQ
pm_qos_update_request(&tegra->boost_cpu_freq_req,
(s32)CONFIG_TEGRA_EHCI_BOOST_CPU_FREQ * 1000);
tegra->cpu_boost_in_work = false;
#endif
mutex_lock(&tegra->sync_lock);
usb_phy_set_suspend(get_usb_phy(tegra->phy), 0);
err = ehci_bus_resume(hcd);
mutex_unlock(&tegra->sync_lock);
EHCI_DBG("%s() END\n", __func__);
return err;
}
static int omap_ehci_bus_resume(struct usb_hcd *hcd)
{
struct ehci_hcd_omap *omap;
unsigned long flags;
int ret = 0;
u32 reg;
omap = ((struct ehci_hcd *)
((char *)hcd_to_ehci(hcd)))->omap_p;
spin_lock_irqsave(&sus_res_lock, flags);
if(omap->suspended){
clk_enable(omap->usbtll_fck);
reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_SHARED_CONF);
reg |=1;
ehci_omap_writel(omap->tll_base, OMAP_TLL_SHARED_CONF, reg);
clk_enable(omap->usbhost_fck);
clk_enable(omap->usbhost_fs_fck);
omap_writel(OHCI_HC_CTRL_RESUME, OHCI_HC_CONTROL);
reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG);
reg &= ~(3 << 12);
reg &= ~(3 << 3);
reg |= (1 << 12);
reg |= (1 << 3);
ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg);
omap->suspended = 0;
ehci_omap_writel(omap->tll_base, OMAP_USBTLL_IRQENABLE, 0);
}
ret = ehci_bus_resume(hcd);
spin_unlock_irqrestore(&sus_res_lock, flags);
return 0;
}
static int ehci_omap_bus_resume(struct usb_hcd *hcd)
{
struct device *dev = hcd->self.controller;
struct ehci_hcd_omap_platform_data *pdata;
struct clk *clk;
int i;
dev_dbg(dev, "ehci_omap_bus_resume\n");
/* Re-enable any external transceiver clocks first */
pdata = dev->platform_data;
for (i = 0 ; i < OMAP3_HS_USB_PORTS ; i++) {
clk = pdata->transceiver_clk[i];
if (clk)
clk_enable(clk);
}
if (dev->parent) {
pm_runtime_get_sync(dev->parent);
}
return ehci_bus_resume(hcd);
}
static int tegra_ehci_bus_resume(struct usb_hcd *hcd)
{
struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
int err = 0;
EHCI_DBG("%s() BEGIN\n", __func__);
#ifdef CONFIG_TEGRA_EHCI_BOOST_CPU_FREQ
tegra->boost_requested = true;
if (pm_qos_request_active(&tegra->boost_cpu_freq_req)
&& tegra->boost_enable) {
schedule_delayed_work(&tegra->boost_cpu_freq_work, 4000);
tegra->cpu_boost_in_work = true;
}
#endif
mutex_lock(&tegra->sync_lock);
usb_phy_set_suspend(get_usb_phy(tegra->phy), 0);
err = ehci_bus_resume(hcd);
mutex_unlock(&tegra->sync_lock);
EHCI_DBG("%s() END\n", __func__);
return err;
}
static int omap_ehci_bus_resume(struct usb_hcd *hcd)
{
return ehci_bus_resume(hcd);
}
static int msm_ehci_bus_resume(struct usb_hcd *hcd)
{
struct ehci_hcd *ehci = hcd_to_ehci (hcd);
u32 temp;
u32 power_okay;
unsigned long resume_needed = 0;
struct msm_hcd *mhcd = hcd_to_mhcd(hcd);
struct msm_usb_host_platform_data *pdata = mhcd->dev->platform_data;
if (mhcd->resume_gpio)
gpio_direction_output(mhcd->resume_gpio, 1);
if(pdata && !pdata->sw_fpr_ctrl) {
ehci_bus_resume(hcd);
} else {
if (time_before (jiffies, ehci->next_statechange))
msleep(5);
spin_lock_irq (&ehci->lock);
if (!HCD_HW_ACCESSIBLE(hcd)) {
spin_unlock_irq(&ehci->lock);
return -ESHUTDOWN;
}
if (unlikely(ehci->debug)) {
if (!dbgp_reset_prep())
ehci->debug = NULL;
else
dbgp_external_startup();
}
/* Ideally and we've got a real resume here, and no port's power
* was lost. (For PCI, that means Vaux was maintained.) But we
* could instead be restoring a swsusp snapshot -- so that BIOS was
* the last user of the controller, not reset/pm hardware keeping
* state we gave to it.
*/
power_okay = ehci_readl(ehci, &ehci->regs->intr_enable);
ehci_dbg(ehci, "resume root hub%s\n",
power_okay ? "" : " after power loss");
/* at least some APM implementations will try to deliver
* IRQs right away, so delay them until we're ready.
*/
ehci_writel(ehci, 0, &ehci->regs->intr_enable);
/* re-init operational registers */
ehci_writel(ehci, 0, &ehci->regs->segment);
ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
ehci_writel(ehci, (u32) ehci->async->qh_dma, &ehci->regs->async_next);
/*CMD_RUN will be set after, PORT_RESUME gets cleared*/
if (ehci->resume_sof_bug){
temp = ehci_readl(ehci, &ehci->regs->port_status [0]);
if (temp & PORT_PE)
ehci->command &= ~CMD_RUN;
}
/* restore CMD_RUN, framelist size, and irq threshold */
ehci_writel(ehci, ehci->command, &ehci->regs->command);
ehci->rh_state = EHCI_RH_RUNNING;
temp = ehci_readl(ehci, &ehci->regs->port_status [0]);
temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
if (test_bit(0, &ehci->bus_suspended) &&
(temp & PORT_SUSPEND)) {
temp |= PORT_RESUME;
set_bit(0, &resume_needed);
}
ehci_writel(ehci, temp, &ehci->regs->port_status [0]);
if (resume_needed && ehci->resume_sof_bug) {
spin_unlock_irq(&ehci->lock);
msleep(20);
spin_lock_irq(&ehci->lock);
temp = ehci_readl(ehci, &ehci->regs->port_status [0]);
temp &= ~(PORT_RWC_BITS | PORT_RESUME);
ehci_writel(ehci, temp, &ehci->regs->port_status [0]);
ehci_writel(ehci, ehci_readl(ehci,
&ehci->regs->command) | CMD_RUN,
&ehci->regs->command);
goto skip_clear_resume;
}
/* msleep for 20ms only if code is trying to resume port */
if (resume_needed) {
spin_unlock_irq(&ehci->lock);
msleep(20);
spin_lock_irq(&ehci->lock);
}
temp = ehci_readl(ehci, &ehci->regs->port_status [0]);
if (test_bit(0, &resume_needed)) {
temp &= ~(PORT_RWC_BITS | PORT_RESUME);
ehci_writel(ehci, temp, &ehci->regs->port_status [0]);
ehci_vdbg (ehci, "resumed port 0\n");
}
skip_clear_resume:
(void) ehci_readl(ehci, &ehci->regs->command);
/* maybe re-activate the schedule(s) */
temp = 0;
if (ehci->async->qh_next.qh)
temp |= CMD_ASE;
if (ehci->periodic_sched)
temp |= CMD_PSE;
if (temp) {
ehci->command |= temp;
ehci_writel(ehci, ehci->command, &ehci->regs->command);
}
ehci->next_statechange = jiffies + msecs_to_jiffies(5);
/* Now we can safely re-enable irqs */
ehci_writel(ehci, INTR_MASK, &ehci->regs->intr_enable);
spin_unlock_irq (&ehci->lock);
ehci_handover_companion_ports(ehci);
}
if (mhcd->resume_gpio)
gpio_direction_output(mhcd->resume_gpio, 0);
return 0;
}
static int ehci_omap_bus_suspend(struct usb_hcd *hcd)
{
int ret;
u32 status;
u32 sysconfig;
unsigned long flags;
struct ehci_hcd *ehci;
struct ehci_hcd_omap_platform_data *pdata;
struct ehci_hcd_omap *omap = dev_get_drvdata(hcd->self.controller);
dev_dbg(hcd->self.controller, "%s %ld %lu\n", __func__,
in_interrupt(), jiffies);
ehci = hcd_to_ehci(hcd);
pdata = omap->dev->dev.platform_data;
/* mask interrupt 77 to avoid race condition with ehci_irq */
/* omap_writel(0x2000, 0x482000CC); */
disable_irq(hcd->irq);
ret = ehci_bus_suspend(hcd);
if (ret) {
enable_irq(hcd->irq);
return ret;
}
/* Put UHH in SmartStandby mode */
sysconfig = ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG);
sysconfig &= ~OMAP_UHH_SYSCONFIG_MIDLEMODE_MASK;
sysconfig |= OMAP_UHH_SYSCONFIG_MIDLEMODE;
ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, sysconfig);
spin_lock_irqsave(&usb_clocks_lock, flags);
if (test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
if (pdata->usbhost_standby_status)
ret = pdata->usbhost_standby_status();
if (ret == 0) {
printk(KERN_ERR "ehci: suspend failed!\n");
ret = -EBUSY;
goto end;
} else
ret = 0;
status = ehci_readl(ehci, &ehci->regs->status);
if (status & INTR_MASK) {
printk(KERN_ERR "ehci: pending irq, resume!\n");
ret = -EBUSY;
goto end;
}
ehci_omap_writel(omap->tll_base, OMAP_TLL_SHARED_CONF,
ehci_omap_readl(omap->tll_base, OMAP_TLL_SHARED_CONF) &
~(1));
/* Enable the interrupt so that the remote-wakeup
* can be detected */
ehci_omap_writel(omap->tll_base, OMAP_USBTLL_IRQSTATUS, 7);
ehci_omap_writel(omap->tll_base, OMAP_USBTLL_IRQENABLE, 1);
/* Put UHH in ForceIdle mode */
sysconfig = ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG);
sysconfig &= ~OMAP_UHH_SYSCONFIG_SIDLEMODE_MASK;
ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, sysconfig);
if (omap->usbhost1_48m_fck)
clk_disable(omap->usbhost1_48m_fck);
if (omap->usbhost2_120m_fck)
clk_disable(omap->usbhost2_120m_fck);
if (omap->usbtll_fck)
clk_disable(omap->usbtll_fck);
clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
LOG_USBHOST_ACTIVITY(aUsbHostDbg, iUsbHostDbg, jiffies);
}
spin_unlock_irqrestore(&usb_clocks_lock, flags);
#ifdef CONFIG_HAS_WAKELOCK
wake_unlock(&ehci->wake_lock_ehci_pm);
#endif
return 0;
end:
/* Put UHH in NoStandby mode */
sysconfig = ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG);
sysconfig &= ~OMAP_UHH_SYSCONFIG_MIDLEMODE_MASK;
sysconfig |= OMAP_UHH_SYSCONFIG_NOSTBYMODE;
ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, sysconfig);
spin_unlock_irqrestore(&usb_clocks_lock, flags);
ehci_bus_resume(hcd);
/* unmask irq 77 */
/* omap_writel(0x2000, 0x482000C8); */
enable_irq(hcd->irq);
return ret;
}
