static void pch_log_wake_source(struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); /* RTC */ if (ps->pm1_sts & RTC_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); /* PCI Express (TODO: determine wake device) */ if (ps->pm1_sts & PCIEXPWAK_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); /* PME */ if(ps->gpe0_sts[GPE0_A] & CSE_PME_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); /* SMBUS Wake */ if (ps->gpe0_sts[GPE0_A] & SMB_WAK_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0); /* ACPI Wake Event - Always Log prev_sleep_state*/ elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state); /* Log GPIO events in set A-D */ pch_log_gpio_gpe(ps->gpe0_sts[GPE0_A], ps->gpe0_en[GPE0_A], 0); pch_log_gpio_gpe(ps->gpe0_sts[GPE0_B], ps->gpe0_en[GPE0_B], 32); pch_log_gpio_gpe(ps->gpe0_sts[GPE0_C], ps->gpe0_en[GPE0_C], 64); pch_log_gpio_gpe(ps->gpe0_sts[GPE0_D], ps->gpe0_en[GPE0_D], 96); }
static void pch_log_standard_gpe(u32 gpe0_sts_reg, u32 gpe0_en_reg) { u32 gpe0_en = inl(get_pmbase() + gpe0_en_reg); u32 gpe0_sts = inl(get_pmbase() + gpe0_sts_reg) & gpe0_en; /* PME (TODO: determine wake device) */ if (gpe0_sts & (1 << 11)) elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); /* Internal PME (TODO: determine wake device) */ if (gpe0_sts & (1 << 13)) elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); /* SMBUS Wake */ if (gpe0_sts & (1 << 7)) elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0); }
static void pch_log_wake_source(struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); /* RTC */ if (ps->pm1_sts & RTC_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); /* PCI Express (TODO: determine wake device) */ if (ps->pm1_sts & PCIEXPWAK_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); /* PME (TODO: determine wake device) */ if (ps->gpe0_sts[GPE_STD] & PME_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); /* Internal PME (TODO: determine wake device) */ if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); /* SMBUS Wake */ if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0); /* GPIO27 */ if (ps->gpe0_sts[GPE_STD] & GP27_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, 27); /* Log GPIO events in set 1-3 */ pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0); pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32); pch_log_gpio_gpe(ps->gpe0_sts[GPE_94_64], ps->gpe0_en[GPE_94_64], 64); }
static void log_wake_events(const struct chipset_power_state *ps) { const uint32_t pcie_wake_mask = PCI_EXP_STS | PCIE_WAKE3_STS | PCIE_WAKE2_STS | PCIE_WAKE1_STS | PCIE_WAKE0_STS; uint32_t gpe0_sts; uint32_t gpio_mask; int i; /* Mask off disabled events. */ gpe0_sts = ps->gpe0_sts & ps->gpe0_en; if (ps->pm1_sts & WAK_STS) { elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, acpi_slp_type == 3 ? 3 : 5); } if (ps->pm1_sts & PWRBTN_STS) { elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); } if (ps->pm1_sts & RTC_STS) { elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); } if (gpe0_sts & PME_B0_EN) { elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); } if (gpe0_sts & pcie_wake_mask) { elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); } gpio_mask = SUS_GPIO_STS0; i = 0; while (gpio_mask) { if (gpio_mask & gpe0_sts) { elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); } gpio_mask <<= 1; i++; } }
static void pch_log_gpe(void) { int i; u16 pmbase = get_pmbase(); u32 gpe0_sts, gpe0_en; int gpe0_high_gpios[] = { [0] = 27, [24] = 17, [25] = 19, [26] = 21, [27] = 22, [28] = 43, [29] = 56, [30] = 57, [31] = 60 }; pch_log_standard_gpe(GPE0_EN, GPE0_STS); /* GPIO 0-15 */ gpe0_en = inw(pmbase + GPE0_EN + 2); gpe0_sts = inw(pmbase + GPE0_STS + 2) & gpe0_en; for (i = 0; i <= 15; i++) { if (gpe0_sts & (1 << i)) elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); } /* * Now check and log upper status bits */ gpe0_en = inl(pmbase + GPE0_EN_2); gpe0_sts = inl(pmbase + GPE0_STS_2) & gpe0_en; for (i = 0; i <= 31; i++) { if (!gpe0_high_gpios[i]) continue; if (gpe0_sts & (1 << i)) elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, gpe0_high_gpios[i]); } }
static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { int i; gpe0_sts &= gpe0_en; for (i = 0; i <= 31; i++) { if (gpe0_sts & (1 << i)) elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); } }
static void pch_log_gpio_gpe(u32 gpe0_sts_reg, u32 gpe0_en_reg, int start) { /* GPE Bank 1 is GPIO 0-31 */ u32 gpe0_en = inl(get_pmbase() + gpe0_en_reg); u32 gpe0_sts = inl(get_pmbase() + gpe0_sts_reg) & gpe0_en; int i; for (i = 0; i <= 31; i++) { if (gpe0_sts & (1 << i)) elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); } }
void pch_log_state(void) { u16 pm1_sts, gen_pmcon_3, tco2_sts; u32 gpe0_sts, gpe0_en; u8 gen_pmcon_2; int i; struct device *lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); if (!lpc) return; pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); gpe0_sts = inl(DEFAULT_PMBASE + GPE0_STS); gpe0_en = inl(DEFAULT_PMBASE + GPE0_EN); tco2_sts = inw(DEFAULT_PMBASE + TCO2_STS); gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2); gen_pmcon_3 = pci_read_config16(lpc, GEN_PMCON_3); /* PWR_FLR Power Failure */ if (gen_pmcon_2 & (1 << 0)) elog_add_event(ELOG_TYPE_POWER_FAIL); /* SUS Well Power Failure */ if (gen_pmcon_3 & (1 << 14)) elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); /* SYS_PWROK Failure */ if (gen_pmcon_2 & (1 << 1)) elog_add_event(ELOG_TYPE_SYS_PWROK_FAIL); /* PWROK Failure */ if (gen_pmcon_2 & (1 << 0)) elog_add_event(ELOG_TYPE_PWROK_FAIL); /* Second TCO Timeout */ if (tco2_sts & (1 << 1)) elog_add_event(ELOG_TYPE_TCO_RESET); /* Power Button Override */ if (pm1_sts & (1 << 11)) elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); /* System Reset Status (reset button pushed) */ if (gen_pmcon_2 & (1 << 4)) elog_add_event(ELOG_TYPE_RESET_BUTTON); /* General Reset Status */ if (gen_pmcon_3 & (1 << 9)) elog_add_event(ELOG_TYPE_SYSTEM_RESET); /* ACPI Wake */ if (pm1_sts & (1 << 15)) elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, acpi_is_wakeup_s3() ? 3 : 5); /* * Wake sources */ /* RTC */ if (pm1_sts & (1 << 10)) elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); /* PCI Express (TODO: determine wake device) */ if (pm1_sts & (1 << 14)) elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); /* PME (TODO: determine wake device) */ if (gpe0_sts & (1 << 13)) elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); /* Internal PME (TODO: determine wake device) */ if (gpe0_sts & (1 << 13)) elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); /* GPIO 0-15 */ for (i = 0; i < 16; i++) { if ((gpe0_sts & (1 << (16+i))) && (gpe0_en & (1 << (16+i)))) elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); } /* SMBUS Wake */ if (gpe0_sts & (1 << 7)) elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0); }
void pch_log_state(void) { u16 pm1_sts, gen_pmcon_3, tco2_sts; u8 gen_pmcon_2; struct device *lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); if (!lpc) return; pm1_sts = inw(get_pmbase() + PM1_STS); tco2_sts = inw(get_pmbase() + TCO2_STS); gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2); gen_pmcon_3 = pci_read_config16(lpc, GEN_PMCON_3); /* PWR_FLR Power Failure */ if (gen_pmcon_2 & (1 << 0)) elog_add_event(ELOG_TYPE_POWER_FAIL); /* SUS Well Power Failure */ if (gen_pmcon_3 & (1 << 14)) elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); /* SYS_PWROK Failure */ if (gen_pmcon_2 & (1 << 1)) elog_add_event(ELOG_TYPE_SYS_PWROK_FAIL); /* PWROK Failure */ if (gen_pmcon_2 & (1 << 0)) elog_add_event(ELOG_TYPE_PWROK_FAIL); /* Second TCO Timeout */ if (tco2_sts & (1 << 1)) elog_add_event(ELOG_TYPE_TCO_RESET); /* Power Button Override */ if (pm1_sts & (1 << 11)) elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); /* System Reset Status (reset button pushed) */ if (gen_pmcon_2 & (1 << 4)) elog_add_event(ELOG_TYPE_RESET_BUTTON); /* General Reset Status */ if (gen_pmcon_3 & (1 << 9)) elog_add_event(ELOG_TYPE_SYSTEM_RESET); /* ACPI Wake */ if (pm1_sts & (1 << 15)) elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, acpi_is_wakeup_s3() ? 3 : 5); /* * Wake sources */ /* Power Button */ if (pm1_sts & (1 << 8)) elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); /* RTC */ if (pm1_sts & (1 << 10)) elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); /* PCI Express (TODO: determine wake device) */ if (pm1_sts & (1 << 14)) elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); /* GPE */ if (pch_is_lp()) pch_lp_log_gpe(); else pch_log_gpe(); }