void setup(void)
{
unsigned char adr, flags, d;
unsigned short i;
unsigned char *p;
_flkey = 0;
/* first disable watchdog */
watchdog_disable();
/* avoid any blocking of RS485 bus */
RS485_ENABLE = RS485_ENABLE_OFF;
/* Port and oscillator configuration */
#if defined(CPU_C8051F120)
SFRPAGE = CONFIG_PAGE;
XBR0 = 0x04; // Enable XBar, UART0 & UART1
XBR1 = 0x00;
XBR2 = 0x44;
#ifdef CLK_25MHZ
/* Select internal quartz oscillator */
SFRPAGE = LEGACY_PAGE;
FLSCL = 0x00; // set flash read time for <25 MHz
SFRPAGE = CONFIG_PAGE;
OSCICN = 0x83; // divide by 1
CLKSEL = 0x00; // select internal oscillator
#else // 98 MHz
/* Select internal quartz oscillator */
SFRPAGE = LEGACY_PAGE;
FLSCL = 0xB0; // set flash read time for 100 MHz
SFRPAGE = CONFIG_PAGE;
OSCICN = 0x83; // divide by 1
CLKSEL = 0x00; // select internal oscillator
PLL0CN |= 0x01;
PLL0DIV = 0x01;
PLL0FLT = 0x01;
PLL0MUL = 0x04;
for (i = 0 ; i < 15; i++); // Wait 5us for initialization
PLL0CN |= 0x02;
for (i = 0 ; i<50000 && ((PLL0CN & 0x10) == 0) ; i++);
CLKSEL = 0x02; // select PLL as sysclk src
#endif
#elif defined(CPU_C8051F020)
XBR0 = 0x04; // Enable UART0 & UART1
XBR1 = 0x00;
XBR2 = 0x44;
/* Select external quartz oscillator */
OSCXCN = 0x67; // Crystal mode, Power Factor 22E6
OSCICN = 0x08; // CLKSL=1 (external)
#elif defined(CPU_C8051F310) || defined(CPU_C8051F320)
XBR0 = 0x01; // Enable RX/TX
XBR1 = 0x40; // Enable crossbar
/* Select internal quartz oscillator */
OSCICN = 0x83; // IOSCEN=1, SYSCLK=24.5 MHz
CLKSEL = 0x00; // derive SYSCLK from internal source
#else
XBR0 = 0x04; // Enable RX/TX
XBR1 = 0x00;
XBR2 = 0x40; // Enable crossbar
PRT0CF = 0x01; // P0.0: TX = Push Pull
PRT1CF = 0x00; // P1
PRT2CF = 0x00; // P2 Open drain for 5V LCD
PRT3CF = 0x20; // P3.5: RS485 enable = Push Pull
/* Select external quartz oscillator */
OSCXCN = 0x67; // Crystal mode, Power Factor 22E6
OSCICN = 0x08; // CLKSL=1 (external)
#endif
#ifdef CFG_HAVE_LCD
lcd_setup();
#endif
#ifdef CFG_HAVE_EMIF
/* initialize external memory interface */
d = emif_init();
/* do memory test on cold start */
SFRPAGE = LEGACY_PAGE;
if (d > 0 && (RSTSRC & 0x02) > 0)
emif_test(d);
#endif
/* start system clock */
sysclock_init();
/* enable watchdog with default timeout */
watchdog_enable(0);
/* enable missing clock detector */
RSTSRC |= 0x04;
/* default LED mode */
for (i=0 ; i<N_LED ; i++)
led_mode(i, 1);
/* initialize all memory */
CSR = 0;
addressed = 0;
flash_param = 0;
flash_program = 0;
flash_allowed = 0;
wrong_cpu = 0;
_flkey = 0;
#ifdef CFG_HAVE_RTC
rtc_set = 0;
#endif
i_in = i_out = n_out = 0;
_cur_sub_addr = 0;
for (i=0 ; i<sizeof(in_buf) ; i++)
in_buf[i] = 0;
for (i=0 ; i<sizeof(out_buf) ; i++)
out_buf[i] = 0;
/* check if we got reset by watchdog */
#if defined(CPU_C8051F120)
SFRPAGE = LEGACY_PAGE;
#endif
WD_RESET = ((RSTSRC & 0x02) == 0 && (RSTSRC & 0x08) > 0);
/* initialize UART(s) */
uart_init(0, BD_115200);
#ifdef CFG_UART1_MSCB
uart_init(1, BD_115200);
#endif
#ifdef CFG_DYN_VARIABLES
setup_variables();
#endif
/* count variables */
for (n_variables = _var_size = 0;; n_variables++) {
_var_size += variables[n_variables].width;
if (variables[n_variables].width == 0)
break;
}
/* check if variables are in xdata and xdata is present */
if (n_variables > 0) {
p = variables[0].ud;
d = *p;
*p = 0x55;
if (*p != 0x55)
wrong_cpu = 1;
*p = 0xAA;
if (*p != 0xAA)
wrong_cpu = 1;
*p = d;
}
/* retrieve EEPROM data */
#ifdef CPU_C8051F120
SFRPAGE = LEGACY_PAGE;
#endif
if ((RSTSRC & 0x02) > 0)
flags = eeprom_retrieve(1); // vars on cold start
else
flags = eeprom_retrieve(0);
if ((flags & (1 << 0)) == 0) {
configured_addr = 0;
/* set initial values */
sys_info.node_addr = 0xFFFF;
sys_info.group_addr = 0xFFFF;
memset(sys_info.node_name, 0, sizeof(sys_info.node_name));
strncpy(sys_info.node_name, node_name, sizeof(sys_info.node_name));
} else
configured_addr = 1;
/* store SVN revision */
sys_info.svn_revision = (svn_rev_main[6]-'0')*1000+
(svn_rev_main[7]-'0')*100+
(svn_rev_main[8]-'0')*10+
(svn_rev_main[9]-'0');
if ((flags & (1 << 1)) == 0) {
/* init variables */
for (i = 0; variables[i].width; i++)
if (!(variables[i].flags & MSCBF_DATALESS)) {
/* do it for each sub-address */
for (adr = 0 ; adr < _n_sub_addr ; adr++) {
memset((char*)variables[i].ud + _var_size*adr, 0, variables[i].width);
}
}
/* call user initialization routine with initialization */
user_init(1);
/* write current variables to flash later in main routine */
configured_vars = 0;
} else {
/* call user initialization routine without initialization */
user_init(0);
configured_vars = 1;
}
/* Blink LEDs */
for (i=0 ; i<N_LED ; i++)
led_blink(i, 3, 150);
}
int main(void)
{
uint32_t lastperiodic = 0;
uint32_t lastarp = 0;
uint8_t i;
sysclk_init();
clock_init();
/* Interrupts aktivieren. */
IE |= (1 << _EA);
io_init();
emif_init();
uart_init();
cp2200_init();
uip_init();
uip_arp_init();
memcpy(uip_ethaddr.addr, mac_addr, sizeof(uip_ethaddr.addr));
tcp_app_init();
udp_app_init();
while(1 > 0) {
uip_len = cp2200_receive(uip_buf, UIP_CONF_BUFFER_SIZE);
if(uip_len > 0) {
if(UIP_BUFFER->type == HTONS(UIP_ETHTYPE_IP)) {
uip_arp_ipin();
uip_input();
if(uip_len > 0) {
uip_arp_out();
cp2200_transmit(uip_buf, uip_len);
}
} else if(UIP_BUFFER->type == HTONS(UIP_ETHTYPE_ARP)) {
uip_arp_arpin();
if(uip_len > 0) {
cp2200_transmit(uip_buf, uip_len);
}
}
} else if((get_clock() - lastperiodic) > CLOCK_TICKS_PER_SECOND / 2) {
lastperiodic = get_clock();
for(i = 0; i < UIP_CONNS; i++) {
uip_periodic(i);
if(uip_len > 0) {
uip_arp_out();
cp2200_transmit(uip_buf, uip_len);
}
}
for(i = 0; i < UIP_UDP_CONNS; i++) {
uip_udp_periodic(i);
if(uip_len > 0) {
uip_arp_out();
cp2200_transmit(uip_buf, uip_len);
}
}
}
if((get_clock() - lastarp) > CLOCK_TICKS_PER_SECOND * 10) {
lastarp = get_clock();
uip_arp_timer();
}
}
return 0;
}
