int main(void) { //ewb((uint8_t*)0x80, erb((uint8_t*)0x80)+1); wdt_enable(WDTO_2S); // Avoid an early reboot clock_prescale_set(clock_div_1); // Disable Clock Division:1->8MHz #ifdef HAS_XRAM init_memory_mapped(); // First initialize the RAM #endif // if we had been restarted by watchdog check the REQ BootLoader byte in the // EEPROM if(bit_is_set(MCUSR,WDRF) && erb(EE_REQBL)) { ewb( EE_REQBL, 0 ); // clear flag start_bootloader(); } while(tx_report); // reboot if the bss is not initialized // Setup the timers. Are needed for watchdog-reset OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 TCCR0B = _BV(CS02); TCCR0A = _BV(WGM01); TIMSK0 = _BV(OCIE0A); TCCR1A = 0; TCCR1B = _BV(CS11) | _BV(WGM12); // Timer1: 1us = 8MHz/8 MCUSR &= ~(1 << WDRF); // Enable the watchdog led_init(); // So we can debug spi_init(); eeprom_init(); USB_Init(); fht_init(); tx_init(); ethernet_init(); #ifdef HAS_FS df_init(&df); fs_init(&fs, df, 0); // needs df_init log_init(); // needs fs_init & rtc_init log_enabled = erb(EE_LOGENABLED); #endif input_handle_func = analyze_ttydata; display_channel = DISPLAY_USB; LED_OFF(); for(;;) { USB_USBTask(); CDC_Task(); RfAnalyze_Task(); Minute_Task(); FastRF_Task(); rf_router_task(); #ifdef HAS_ASKSIN rf_asksin_task(); #endif #ifdef HAS_ETHERNET Ethernet_Task(); #endif } }
int main(void) { u2_init(); #ifdef BOOTLOADER putstr("\nUSRP N210 UDP bootloader\n"); #else putstr("\nTxRx-UHD-ZPU\n"); #endif printf("FPGA compatibility number: %d\n", USRP2_FPGA_COMPAT_NUM); printf("Firmware compatibility number: %d\n", USRP2_FW_COMPAT_NUM); #ifdef BOOTLOADER //load the production FPGA image or firmware if appropriate do_the_bootload_thing(); //if we get here we've fallen through to safe firmware set_default_mac_addr(); set_default_ip_addr(); #endif print_mac_addr(ethernet_mac_addr()); newline(); print_ip_addr(get_ip_addr()); newline(); //1) register the addresses into the network stack register_addrs(ethernet_mac_addr(), get_ip_addr()); pkt_ctrl_program_inspector(get_ip_addr(), USRP2_UDP_DSP0_PORT); //2) register callbacks for udp ports we service init_udp_listeners(); register_udp_listener(USRP2_UDP_CTRL_PORT, handle_udp_ctrl_packet); register_udp_listener(USRP2_UDP_DSP0_PORT, handle_udp_data_packet); register_udp_listener(USRP2_UDP_ERR0_PORT, handle_udp_data_packet); register_udp_listener(USRP2_UDP_DSP1_PORT, handle_udp_data_packet); #ifdef USRP2P register_udp_listener(USRP2_UDP_UPDATE_PORT, handle_udp_fw_update_packet); #endif //3) set the routing mode to slave to set defaults pkt_ctrl_set_routing_mode(PKT_CTRL_ROUTING_MODE_SLAVE); //4) setup ethernet hardware to bring the link up ethernet_register_link_changed_callback(link_changed_callback); ethernet_init(); while(true){ size_t num_lines; void *buff = pkt_ctrl_claim_incoming_buffer(&num_lines); if (buff != NULL){ handle_inp_packet((uint32_t *)buff, num_lines); pkt_ctrl_release_incoming_buffer(); } pic_interrupt_handler(); int pending = pic_regs->pending; // poll for under or overrun if (pending & PIC_UNDERRUN_INT){ pic_regs->pending = PIC_UNDERRUN_INT; // clear interrupt putchar('U'); } if (pending & PIC_OVERRUN_INT){ pic_regs->pending = PIC_OVERRUN_INT; // clear interrupt putchar('O'); } } }
int main(void) { u2_init(); putstr("\nFactory Test\n"); print_mac_addr(ethernet_mac_addr()->addr); newline(); if(test_sd()) puts("SD OK\n"); else { puts("SD FAIL\n"); // hal_finish(); //return 0; } if(test_ram()) puts("RAM OK\n"); else { puts("RAM FAIL\n"); hal_finish(); return 0; } print_mac_addr(ethernet_mac_addr()->addr); newline(); output_regs->led_src = 0x7; // make bottom 3 controlled by HW ethernet_register_link_changed_callback(link_changed_callback); ethernet_init(); clocks_enable_tx_dboard(true,1); clocks_mimo_config(MC_WE_LOCK_TO_SMA); #if 0 // make bit 15 of Tx gpio's be a s/w output hal_gpio_set_sel(GPIO_TX_BANK, 15, 's'); hal_gpio_set_ddr(GPIO_TX_BANK, 0x8000, 0x8000); #endif output_regs->debug_mux_ctrl = 1; #if 0 hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111"); hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111"); hal_gpio_set_ddr(GPIO_TX_BANK, 0xffff, 0xffff); hal_gpio_set_ddr(GPIO_RX_BANK, 0xffff, 0xffff); #endif // initialize double buffering state machine for ethernet -> DSP Tx dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0, &dsp_tx_recv_args, &dsp_tx_send_args, eth_pkt_inspector); // initialize double buffering state machine for DSP RX -> Ethernet if (FW_SETS_SEQNO){ dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0, &dsp_rx_recv_args, &dsp_rx_send_args, fw_sets_seqno_inspector); } else { dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0, &dsp_rx_recv_args, &dsp_rx_send_args, dbsm_nop_inspector); } // tell app_common that this dbsm could be sending to the ethernet ac_could_be_sending_to_eth = &dsp_rx_sm; // program tx registers setup_tx(); // kick off the state machine dbsm_start(&dsp_tx_sm); //int which = 0; while(1){ // hal_gpio_write(GPIO_TX_BANK, which, 0x8000); // which ^= 0x8000; buffer_irq_handler(0); int pending = pic_regs->pending; // poll for under or overrun if (pending & PIC_UNDERRUN_INT){ dbsm_handle_tx_underrun(&dsp_tx_sm); pic_regs->pending = PIC_UNDERRUN_INT; // clear interrupt putchar('U'); } if (pending & PIC_OVERRUN_INT){ dbsm_handle_rx_overrun(&dsp_rx_sm); pic_regs->pending = PIC_OVERRUN_INT; // clear pending interrupt // FIXME Figure out how to handle this robustly. // Any buffers that are emptying should be allowed to drain... if (streaming_p){ // restart_streaming(); // FIXME report error } else { // FIXME report error } putchar('O'); } } }