static void export_vrml_drawings( MODEL_VRML& aModel, BOARD* pcb ) { // draw graphic items for( EDA_ITEM* drawing = pcb->m_Drawings; drawing != 0; drawing = drawing->Next() ) { LAYER_ID layer = ( (DRAWSEGMENT*) drawing )->GetLayer(); if( layer != F_Cu && layer != B_Cu && layer != B_SilkS && layer != F_SilkS ) continue; switch( drawing->Type() ) { case PCB_LINE_T: export_vrml_drawsegment( aModel, (DRAWSEGMENT*) drawing ); break; case PCB_TEXT_T: export_vrml_pcbtext( aModel, (TEXTE_PCB*) drawing ); break; default: break; } } }
static void export_vrml_drawings( BOARD* pcb ) //{{{ { // draw graphic items for( EDA_ITEM* drawing = pcb->m_Drawings; drawing != 0; drawing = drawing->Next() ) { switch( drawing->Type() ) { case PCB_LINE_T: export_vrml_drawsegment( (DRAWSEGMENT*) drawing ); break; case PCB_TEXT_T: export_vrml_pcbtext( (TEXTE_PCB*) drawing ); break; default: break; } } }