static void export_vrml_tracks( BOARD* pcb ) //{{{ { for( TRACK* track = pcb->m_Track; track != NULL; track = track->Next() ) { if( track->Type() == PCB_VIA_T ) export_vrml_via( pcb, (SEGVIA*) track ); else export_vrml_line( track->GetLayer(), track->GetStart().x, track->GetStart().y, track->GetEnd().x, track->GetEnd().y, track->GetWidth(), 4 ); } }
static void export_vrml_tracks( MODEL_VRML& aModel, BOARD* pcb ) { for( TRACK* track = pcb->m_Track; track; track = track->Next() ) { if( track->Type() == PCB_VIA_T ) { export_vrml_via( aModel, pcb, (const VIA*) track ); } else if( track->GetLayer() == B_Cu || track->GetLayer() == F_Cu ) export_vrml_line( aModel, track->GetLayer(), track->GetStart().x * aModel.scale, track->GetStart().y * aModel.scale, track->GetEnd().x * aModel.scale, track->GetEnd().y * aModel.scale, track->GetWidth() * aModel.scale ); } }