void timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *clk)
{
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
if (timer_cs_used == -1)
return;
ext_timer_stop(timer_ce_used);
/* set up timer based on HZ given, unit is msec */
ext_timer_set_period(timer_ce_used, 1000000/HZ);
ext_timer_set_mode(timer_ce_used, EXT_TIMER_MODE_PERIODIC);
ext_timer_start(timer_ce_used);
break;
case CLOCK_EVT_MODE_ONESHOT:
/* timer is set and enabled in 'set_next_event' hook */
break;
case CLOCK_EVT_MODE_RESUME:
ext_timer_start(timer_ce_used);
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
ext_timer_stop(timer_ce_used);
default:
break;
}
}
static void ext_timer_ctrl(enum ext_timer_sel ext_timer,
enum ext_timer_clock_source ext_timer_clock,
int start,
int with_int,
int32_t count)
{
uint8_t intc_mask;
/* rising-edge-triggered */
intc_mask = et_ctrl_regs[ext_timer].mask;
*et_ctrl_regs[ext_timer].mode |= intc_mask;
*et_ctrl_regs[ext_timer].polarity &= ~intc_mask;
/* clear interrupt status */
task_clear_pending_irq(et_ctrl_regs[ext_timer].irq);
/* These bits control the clock input source to the exttimer 3 - 8 */
IT83XX_ETWD_ETXPSR(ext_timer) = ext_timer_clock;
/* The count number of external timer n. */
IT83XX_ETWD_ETXCNTLR(ext_timer) = count;
ext_timer_stop(ext_timer, 0);
if (start)
ext_timer_start(ext_timer, 0);
if (with_int)
task_enable_irq(et_ctrl_regs[ext_timer].irq);
else
task_disable_irq(et_ctrl_regs[ext_timer].irq);
}
int timer_set_next_event(unsigned long cycle,
struct clock_event_device *unused)
{
if (timer_cs_used == -1)
return -ENODEV;
/* stop the timer will clear the residual counter */
ext_timer_stop(timer_ce_used);
ext_timer_set_count(timer_ce_used, cycle);
ext_timer_set_mode(timer_ce_used, EXT_TIMER_MODE_ONESHOT);
ext_timer_start(timer_ce_used);
return 0;
}
static void __init periph_timer_clocksource_init(void)
{
if (timer_cs_used != -1)
return;
timer_cs_used = ext_timer_alloc(-1, PERIPH_TIMER_PERIOD_MAX, NULL, 0);
/* cannot allocate timer, just quit. Shouldn't happen! */
if (timer_cs_used == -1)
return;
ext_timer_start(timer_cs_used);
/* bcm63xx_clocksource->shift/mult will be computed by the following
* register function */
clocksource_register_khz(&bcm63xx_clocksource, PERIPH_TIMER_CLK_FREQ);
}
int ext_timer_ms(enum ext_timer_sel ext_timer,
enum ext_timer_clock_source ext_timer_clock,
int start,
int with_int,
int32_t ms,
int first_time_enable,
int raw)
{
uint32_t count;
if (raw) {
count = ms;
} else {
if (ext_timer_clock == EXT_PSR_32P768K_HZ)
count = MS_TO_COUNT(32768, ms);
else if (ext_timer_clock == EXT_PSR_1P024K_HZ)
count = MS_TO_COUNT(1024, ms);
else if (ext_timer_clock == EXT_PSR_32_HZ)
count = MS_TO_COUNT(32, ms);
else if (ext_timer_clock == EXT_PSR_8M_HZ)
count = 8000 * ms;
else
return -1;
}
if (count == 0)
return -3;
if (first_time_enable) {
ext_timer_start(ext_timer, 0);
ext_timer_stop(ext_timer, 0);
}
ext_timer_ctrl(ext_timer, ext_timer_clock, start, with_int, count);
return 0;
}
