コード例 #1
0
ファイル: exynos_dp_core.c プロジェクト: AshishKumar4/linux
static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
{
	int lane, lane_count, retval;
	u32 reg;
	u8 link_align, link_status[2], adjust_request[2];

	usleep_range(400, 401);

	lane_count = dp->link_train.lane_count;

	retval = exynos_dp_read_bytes_from_dpcd(dp,
			DP_LANE0_1_STATUS, 2, link_status);
	if (retval)
		return retval;

	if (exynos_dp_clock_recovery_ok(link_status, lane_count)) {
		exynos_dp_reduce_link_rate(dp);
		return -EIO;
	}

	retval = exynos_dp_read_bytes_from_dpcd(dp,
			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
	if (retval)
		return retval;

	retval = exynos_dp_read_byte_from_dpcd(dp,
			DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
	if (retval)
		return retval;

	exynos_dp_get_adjust_training_lane(dp, adjust_request);

	if (!exynos_dp_channel_eq_ok(link_status, link_align, lane_count)) {
		/* traing pattern Set to Normal */
		exynos_dp_training_pattern_dis(dp);

		dev_info(dp->dev, "Link Training success!\n");

		exynos_dp_get_link_bandwidth(dp, &reg);
		dp->link_train.link_rate = reg;
		dev_dbg(dp->dev, "final bandwidth = %.2x\n",
			dp->link_train.link_rate);

		exynos_dp_get_lane_count(dp, &reg);
		dp->link_train.lane_count = reg;
		dev_dbg(dp->dev, "final lane count = %.2x\n",
			dp->link_train.lane_count);

		/* set enhanced mode if available */
		exynos_dp_set_enhanced_mode(dp);
		dp->link_train.lt_state = FINISHED;

		return 0;
	}

	/* not all locked 
コード例 #2
0
ファイル: exynos_dp_core.c プロジェクト: Red680812/DNA_kitkat
static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
{
    u8 link_status[6];
    int lane;
    int lane_count;
    u8 buf[5];
    u32 reg;

    u8 *adjust_request;

    udelay(400);

    exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
                                   6, link_status);
    lane_count = dp->link_train.lane_count;

    if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
        adjust_request = link_status + (DPCD_ADDR_ADJUST_REQUEST_LANE0_1
                                        - DPCD_ADDR_LANE0_1_STATUS);

        if (exynos_dp_channel_eq_ok(link_status, lane_count) == 0) {
            /* traing pattern Set to Normal */
            exynos_dp_training_pattern_dis(dp);

            dev_info(dp->dev, "Link Training success!\n");

            exynos_dp_get_link_bandwidth(dp, &reg);
            dp->link_train.link_rate = reg;
            dev_dbg(dp->dev, "final bandwidth = %.2x\n",
                    dp->link_train.link_rate);

            exynos_dp_get_lane_count(dp, &reg);
            dp->link_train.lane_count = reg;
            dev_dbg(dp->dev, "final lane count = %.2x\n",
                    dp->link_train.lane_count);
            /* set enhanced mode if available */
            exynos_dp_set_enhanced_mode(dp);

            dp->link_train.lt_state = FINISHED;
        } else {
            /* not all locked */
            dp->link_train.eq_loop++;

            if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
                exynos_dp_reduce_link_rate(dp);
            } else {
                exynos_dp_get_adjust_train(dp, adjust_request);

                for (lane = 0; lane < lane_count; lane++) {
                    exynos_dp_set_lane_link_training(dp,
                                                     dp->link_train.training_lane[lane],
                                                     lane);
                    buf[lane] = dp->link_train.training_lane[lane];
                    exynos_dp_write_byte_to_dpcd(dp,
                                                 DPCD_ADDR_TRAINING_LANE0_SET + lane,
                                                 buf[lane]);
                }
            }
        }
    } else {
        exynos_dp_reduce_link_rate(dp);
    }

    return 0;
}
コード例 #3
0
ファイル: exynos_dp_core.c プロジェクト: AllenDou/linux
static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
{
	u8 link_status[2];
	u8 link_align[3];
	int lane;
	int lane_count;
	u32 reg;

	u8 adjust_request[2];
	u8 voltage_swing;
	u8 pre_emphasis;
	u8 training_lane;

	usleep_range(400, 401);

	lane_count = dp->link_train.lane_count;

	exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
				2, link_status);

	if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
		link_align[0] = link_status[0];
		link_align[1] = link_status[1];

		exynos_dp_read_byte_from_dpcd(dp,
			DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED,
			&link_align[2]);

		for (lane = 0; lane < lane_count; lane++) {
			exynos_dp_read_bytes_from_dpcd(dp,
					DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
					2, adjust_request);
			voltage_swing = exynos_dp_get_adjust_request_voltage(
							adjust_request, lane);
			pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
							adjust_request, lane);
			training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
					DPCD_PRE_EMPHASIS_SET(pre_emphasis);

			if (voltage_swing == VOLTAGE_LEVEL_3)
				training_lane |= DPCD_MAX_SWING_REACHED;
			if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
				training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;

			dp->link_train.training_lane[lane] = training_lane;
		}

		if (exynos_dp_channel_eq_ok(link_align, lane_count) == 0) {
			/* traing pattern Set to Normal */
			exynos_dp_training_pattern_dis(dp);

			dev_info(dp->dev, "Link Training success!\n");

			exynos_dp_get_link_bandwidth(dp, &reg);
			dp->link_train.link_rate = reg;
			dev_dbg(dp->dev, "final bandwidth = %.2x\n",
				dp->link_train.link_rate);

			exynos_dp_get_lane_count(dp, &reg);
			dp->link_train.lane_count = reg;
			dev_dbg(dp->dev, "final lane count = %.2x\n",
				dp->link_train.lane_count);

			/* set enhanced mode if available */
			exynos_dp_set_enhanced_mode(dp);
			dp->link_train.lt_state = FINISHED;
		} else {
			/* not all locked */
			dp->link_train.eq_loop++;

			if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
				dev_err(dp->dev, "EQ Max loop\n");
				goto reduce_link_rate;
			}

			for (lane = 0; lane < lane_count; lane++)
				exynos_dp_set_lane_link_training(dp,
					dp->link_train.training_lane[lane],
					lane);

			exynos_dp_write_bytes_to_dpcd(dp,
				DPCD_ADDR_TRAINING_LANE0_SET,
				lane_count,
				dp->link_train.training_lane);
		}
	} else {
		goto reduce_link_rate;
	}

	return 0;

reduce_link_rate:
	exynos_dp_reduce_link_rate(dp);
	return -EIO;
}