void exynos_dp_reset(void) { u32 reg_func_1; /*dp tx sw reset*/ lwrite32(RESET_DP_TX, &dp_regs->tx_sw_reset); exynos_dp_enable_video_input(DP_DISABLE); exynos_dp_disable_video_bist(); exynos_dp_enable_video_mute(DP_DISABLE); /* software reset */ reg_func_1 = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | HDCP_FUNC_EN_N | SW_FUNC_EN_N; lwrite32(reg_func_1, &dp_regs->func_en1); lwrite32(reg_func_1, &dp_regs->func_en2); mdelay(1); exynos_dp_init_analog_param(); exynos_dp_init_interrupt(); return; }
static void exynos_dp_init_dp(struct exynos_dp_device *dp) { exynos_dp_reset(dp); exynos_dp_swreset(dp); exynos_dp_init_analog_param(dp); exynos_dp_init_interrupt(dp); /* SW defined function Normal operation */ exynos_dp_enable_sw_function(dp); exynos_dp_config_interrupt(dp); exynos_dp_init_analog_func(dp); exynos_dp_init_hpd(dp); exynos_dp_init_aux(dp); }