int board_eth_init(bd_t *bis) { struct mxs_clkctrl_regs *clkctrl_regs = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; struct eth_device *dev; int ret; ret = cpu_eth_init(bis); /* MX28EVK uses ENET_CLK PAD to drive FEC clock */ writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, &clkctrl_regs->hw_clkctrl_enet); /* Power-on FECs */ gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0); /* Reset FEC PHYs */ gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0); udelay(200); gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1); ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); if (ret) { puts("FEC MXS: Unable to init FEC0\n"); return ret; } ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE); if (ret) { puts("FEC MXS: Unable to init FEC1\n"); return ret; } dev = eth_get_dev_by_name("FEC0"); if (!dev) { puts("FEC MXS: Unable to get FEC0 device entry\n"); return -EINVAL; } ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); if (ret) { puts("FEC MXS: Unable to register FEC0 mii postcall\n"); return ret; } dev = eth_get_dev_by_name("FEC1"); if (!dev) { puts("FEC MXS: Unable to get FEC1 device entry\n"); return -EINVAL; } ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); if (ret) { puts("FEC MXS: Unable to register FEC1 mii postcall\n"); return ret; } return ret; }
int board_eth_init(bd_t *bis) { setup_iomux_fec(CONFIG_FEC_ENET_DEV); return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); }
int board_eth_init(bd_t *bis) { int ret; setup_iomux_fec(CONFIG_FEC_ENET_DEV); ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); if (ret) printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__); return 0; }
int board_eth_init(bd_t *bis) { int ret; imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); setup_fec(); ret = fecmxc_initialize_multi(bis, 1, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); if (ret) printf("FEC%d MXC: %s:failed\n", 1, __func__); return ret; }
int board_eth_init(bd_t *bis) { /* set Ethernet MAC address environment */ cl_som_imx7_handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS); /* Ethernet interface pinmux configuration */ cl_som_imx7_phy1_rst_pads_set(); cl_som_imx7_fec1_pads_set(); /* PHY reset */ gpio_request(CL_SOM_IMX7_ETH1_PHY_NRST, "eth1_phy_nrst"); gpio_direction_output(CL_SOM_IMX7_ETH1_PHY_NRST, 0); mdelay(10); gpio_set_value(CL_SOM_IMX7_ETH1_PHY_NRST, 1); /* MAC initialization */ return fecmxc_initialize_multi(bis, CL_SOM_IMX7_FEC_DEV_ID_PRI, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); }
int board_eth_init(bd_t *bis) { struct mxs_clkctrl_regs *clkctrl_regs = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; struct eth_device *dev; int ret; ret = cpu_eth_init(bis); if (ret) return ret; clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN, CLKCTRL_ENET_TIME_SEL_RMII_CLK); #if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10) /* Reset the new PHY */ gpio_direction_output(MX28_PAD_AUART2_RTS__GPIO_3_11, 0); udelay(10000); gpio_set_value(MX28_PAD_AUART2_RTS__GPIO_3_11, 1); udelay(10000); #endif ret = fecmxc_initialize_multi(bis, 0, 1 << 0, MXS_ENET0_BASE); if (ret) { printf("FEC MXS: Unable to init FEC0\n"); return ret; } ret = fecmxc_initialize_multi(bis, 1, 1 << 3, MXS_ENET1_BASE); if (ret) { printf("FEC MXS: Unable to init FEC1\n"); return ret; } dev = eth_get_dev_by_name("FEC0"); if (!dev) { printf("FEC MXS: Unable to get FEC0 device entry\n"); return -EINVAL; } ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); if (ret) { printf("FEC MXS: Unable to register FEC0 mii postcall\n"); return ret; } dev = eth_get_dev_by_name("FEC1"); if (!dev) { printf("FEC MXS: Unable to get FEC1 device entry\n"); return -EINVAL; } ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); if (ret) { printf("FEC MXS: Unable to register FEC1 mii postcall\n"); return ret; } return ret; }
int fecmxc_initialize(bd_t *bd) { return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); }
int board_eth_init(bd_t *bis) { int ret; /* Reset the external phy */ gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0); /* Power on the external phy */ gpio_direction_output(MX28_PAD_PWM4__GPIO_3_29, 1); /* Pull strap pins to high */ gpio_direction_output(MX28_PAD_ENET0_RX_EN__GPIO_4_2, 1); gpio_direction_output(MX28_PAD_ENET0_RXD0__GPIO_4_3, 1); gpio_direction_output(MX28_PAD_ENET0_RXD1__GPIO_4_4, 1); gpio_direction_input(MX28_PAD_ENET0_TX_CLK__GPIO_4_5); udelay(25000); gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1); udelay(100); mxs_iomux_setup_multiple_pads(tx28_fec_pads, ARRAY_SIZE(tx28_fec_pads)); ret = cpu_eth_init(bis); if (ret) { printf("cpu_eth_init() failed: %d\n", ret); return ret; } ret = fec_get_mac_addr(0); if (ret < 0) { printf("Failed to read FEC0 MAC address from OCOTP\n"); return ret; } #ifdef CONFIG_FEC_MXC_MULTI if (getenv("ethaddr")) { ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); if (ret) { printf("FEC MXS: Unable to init FEC0\n"); return ret; } } ret = fec_get_mac_addr(1); if (ret < 0) { printf("Failed to read FEC1 MAC address from OCOTP\n"); return ret; } if (getenv("eth1addr")) { ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE); if (ret) { printf("FEC MXS: Unable to init FEC1\n"); return ret; } } return 0; #else if (getenv("ethaddr")) { ret = fecmxc_initialize(bis); } return ret; #endif }