int board_eth_init(bd_t *bis) { struct mxs_clkctrl_regs *clkctrl_regs = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; struct eth_device *dev; int ret; ret = cpu_eth_init(bis); /* MX28EVK uses ENET_CLK PAD to drive FEC clock */ writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, &clkctrl_regs->hw_clkctrl_enet); /* Power-on FECs */ gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0); /* Reset FEC PHYs */ gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0); udelay(200); gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1); ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); if (ret) { puts("FEC MXS: Unable to init FEC0\n"); return ret; } ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE); if (ret) { puts("FEC MXS: Unable to init FEC1\n"); return ret; } dev = eth_get_dev_by_name("FEC0"); if (!dev) { puts("FEC MXS: Unable to get FEC0 device entry\n"); return -EINVAL; } ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); if (ret) { puts("FEC MXS: Unable to register FEC0 mii postcall\n"); return ret; } dev = eth_get_dev_by_name("FEC1"); if (!dev) { puts("FEC MXS: Unable to get FEC1 device entry\n"); return -EINVAL; } ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); if (ret) { puts("FEC MXS: Unable to register FEC1 mii postcall\n"); return ret; } return ret; }
int board_eth_init(bd_t *bis) { struct eth_device *dev; int ret; ret = cpu_eth_init(bis); if (ret) { printf("FEC MXC: %s:failed\n", __func__); return ret; } dev = eth_get_dev_by_name("FEC"); if (!dev) { printf("FEC MXC: Unable to get FEC device entry\n"); return -EINVAL; } ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); if (ret) { printf("FEC MXC: Unable to register FEC mii postcall\n"); return ret; } return 0; }
int board_eth_init(bd_t *bis) { int ret; struct eth_device *dev; ret = cpu_eth_init(bis); if (ret) { printf("FEC MXS: Unable to init FEC clocks\n"); return ret; } ret = fecmxc_initialize(bis); if (ret) { printf("FEC MXS: Unable to init FEC\n"); return ret; } dev = eth_get_dev_by_name("FEC"); if (!dev) { printf("FEC MXS: Unable to get FEC device entry\n"); return -EINVAL; } ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); if (ret) { printf("FEC MXS: Unable to register FEC MII postcall\n"); return ret; } return ret; }
int board_eth_init(bd_t *bis) { struct mxs_clkctrl_regs *clkctrl_regs = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; struct eth_device *dev; int ret; ret = cpu_eth_init(bis); if (ret) return ret; clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN, CLKCTRL_ENET_TIME_SEL_RMII_CLK); #if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10) /* Reset the new PHY */ gpio_direction_output(MX28_PAD_AUART2_RTS__GPIO_3_11, 0); udelay(10000); gpio_set_value(MX28_PAD_AUART2_RTS__GPIO_3_11, 1); udelay(10000); #endif ret = fecmxc_initialize_multi(bis, 0, 1 << 0, MXS_ENET0_BASE); if (ret) { printf("FEC MXS: Unable to init FEC0\n"); return ret; } ret = fecmxc_initialize_multi(bis, 1, 1 << 3, MXS_ENET1_BASE); if (ret) { printf("FEC MXS: Unable to init FEC1\n"); return ret; } dev = eth_get_dev_by_name("FEC0"); if (!dev) { printf("FEC MXS: Unable to get FEC0 device entry\n"); return -EINVAL; } ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); if (ret) { printf("FEC MXS: Unable to register FEC0 mii postcall\n"); return ret; } dev = eth_get_dev_by_name("FEC1"); if (!dev) { printf("FEC MXS: Unable to get FEC1 device entry\n"); return -EINVAL; } ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); if (ret) { printf("FEC MXS: Unable to register FEC1 mii postcall\n"); return ret; } return ret; }