static void __init omap_uart_init_preirq(struct serial_port *port)
{
struct omap_uart *uart = port->uart;
/*
* Clear the FIFO buffers.
*/
omap_write(uart, UART_FCR, UART_FCR_ENABLE);
omap_write(uart, UART_FCR, UART_FCR_ENABLE|UART_FCR_CLRX|UART_FCR_CLTX);
omap_write(uart, UART_FCR, 0);
/*
* The TRM says the mode should be disabled while UART_DLL and UART_DHL
* are being changed so we disable before setup, then enable.
*/
omap_write(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
/* Baud rate & protocol format setup */
baud_protocol_setup(uart);
/* FIFO setup */
fifo_setup(uart);
/* No flow control */
omap_write(uart, UART_MCR, UART_MCR_DTR|UART_MCR_RTS);
omap_write(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
/* setup idle mode */
omap_write(uart, UART_OMAP_SYSC, UART_OMAP_SYSC_DEF_CONF);
}
static void comms_stream_setup(comms_stream_struct *cs, uint8_t *tx_fifo_buffer, uint8_t tx_fifo_length, uint8_t *rx_fifo_buffer, uint8_t rx_fifo_length, uint8_t *command_bytes, uint8_t command_bytes_max_length)
{
fifo_setup(&(cs->tx_fifo), tx_fifo_buffer, tx_fifo_length);
fifo_setup(&(cs->rx_fifo), rx_fifo_buffer, rx_fifo_length);
cs->scan_state = 0;
cs->unknown_start_bytes = FALSE;
cs->rx_packet_errors = 0;
cs->command_bytes = command_bytes;
cs->command_bytes_max_length = command_bytes_max_length;
cs->command_bytes_available = 0;
// cs->is_single_class should be set by command source itself (i.e. from start byte of incoming comms packet)
// however, if this does not dynamically change default to cs->is_single_class is FALSE
cs->is_single_class = FALSE;
}
static int ilo_ccb_setup(struct ilo_hwinfo *hw, struct ccb_data *data, int slot)
{
char *dma_va;
dma_addr_t dma_pa;
struct ccb *driver_ccb, *ilo_ccb;
driver_ccb = &data->driver_ccb;
ilo_ccb = &data->ilo_ccb;
data->dma_size = 2 * fifo_sz(NR_QENTRY) +
2 * desc_mem_sz(NR_QENTRY) +
ILO_START_ALIGN + ILO_CACHE_SZ;
data->dma_va = pci_alloc_consistent(hw->ilo_dev, data->dma_size,
&data->dma_pa);
if (!data->dma_va)
return -ENOMEM;
dma_va = (char *)data->dma_va;
dma_pa = data->dma_pa;
memset(dma_va, 0, data->dma_size);
dma_va = (char *)roundup((unsigned long)dma_va, ILO_START_ALIGN);
dma_pa = roundup(dma_pa, ILO_START_ALIGN);
/*
* Create two ccb's, one with virt addrs, one with phys addrs.
* Copy the phys addr ccb to device shared mem.
*/
ctrl_setup(driver_ccb, NR_QENTRY, L2_QENTRY_SZ);
ctrl_setup(ilo_ccb, NR_QENTRY, L2_QENTRY_SZ);
fifo_setup(dma_va, NR_QENTRY);
driver_ccb->ccb_u1.send_fifobar = dma_va + FIFOHANDLESIZE;
ilo_ccb->ccb_u1.send_fifobar_pa = dma_pa + FIFOHANDLESIZE;
dma_va += fifo_sz(NR_QENTRY);
dma_pa += fifo_sz(NR_QENTRY);
dma_va = (char *)roundup((unsigned long)dma_va, ILO_CACHE_SZ);
dma_pa = roundup(dma_pa, ILO_CACHE_SZ);
fifo_setup(dma_va, NR_QENTRY);
driver_ccb->ccb_u3.recv_fifobar = dma_va + FIFOHANDLESIZE;
ilo_ccb->ccb_u3.recv_fifobar_pa = dma_pa + FIFOHANDLESIZE;
dma_va += fifo_sz(NR_QENTRY);
dma_pa += fifo_sz(NR_QENTRY);
driver_ccb->ccb_u2.send_desc = dma_va;
ilo_ccb->ccb_u2.send_desc_pa = dma_pa;
dma_pa += desc_mem_sz(NR_QENTRY);
dma_va += desc_mem_sz(NR_QENTRY);
driver_ccb->ccb_u4.recv_desc = dma_va;
ilo_ccb->ccb_u4.recv_desc_pa = dma_pa;
driver_ccb->channel = slot;
ilo_ccb->channel = slot;
driver_ccb->ccb_u5.db_base = hw->db_vaddr + (slot << L2_DB_SIZE);
ilo_ccb->ccb_u5.db_base = NULL; /* hw ccb's doorbell is not used */
return 0;
}
