コード例 #1
0
static int fimc_is_isp_video_s_ctrl(struct file *file, void *priv,
					struct v4l2_control *ctrl)
{
	int ret = 0;
	int i2c_clk;
	struct fimc_is_video *video;
	struct fimc_is_video_ctx *vctx = file->private_data;
	struct fimc_is_device_ischain *device;
	struct fimc_is_core *core;

	BUG_ON(!vctx);
	BUG_ON(!vctx->device);
	BUG_ON(!vctx->video);

	dbg_isp("%s\n", __func__);

	device = vctx->device;
	video = vctx->video;
	core = container_of(video, struct fimc_is_core, video_isp);

	if (core->resourcemgr.dvfs_ctrl.cur_int_qos == DVFS_L0)
		i2c_clk = I2C_L0;
	else
		i2c_clk = I2C_L1;

	switch (ctrl->id) {
	case V4L2_CID_IS_DEBUG_DUMP:
		info("Print fimc-is info dump by HAL");
		if (device != NULL) {
			fimc_is_hw_logdump(device->interface);
			fimc_is_hw_regdump(device->interface);
			CALL_POPS(device, print_clk, device->pdev);
		}
		if (ctrl->value) {
			err("BUG_ON from HAL");
			BUG();
		}
		break;
	case V4L2_CID_IS_DEBUG_SYNC_LOG:
		fimc_is_logsync(device->interface, ctrl->value, IS_MSG_TEST_SYNC_LOG);
		break;
	case V4L2_CID_IS_HAL_VERSION:
		if (ctrl->value < 0 || ctrl->value >= IS_HAL_VER_MAX) {
			merr("hal version(%d) is invalid", vctx, ctrl->value);
			ret = -EINVAL;
			goto p_err;
		}
		core->resourcemgr.hal_version = ctrl->value;
		break;
	case V4L2_CID_IS_G_CAPABILITY:
		ret = fimc_is_ischain_g_capability(device, ctrl->value);
		dbg_isp("V4L2_CID_IS_G_CAPABILITY : %X\n", ctrl->value);
		break;
	case V4L2_CID_IS_FORCE_DONE:
		set_bit(FIMC_IS_GROUP_REQUEST_FSTOP, &device->group_isp.state);
		break;
	case V4L2_CID_IS_DVFS_LOCK:
		ret = fimc_is_itf_i2c_lock(device, I2C_L0, true);
		if (ret) {
			err("fimc_is_itf_i2_clock fail\n");
			break;
		}
		pm_qos_add_request(&device->user_qos, PM_QOS_DEVICE_THROUGHPUT,
					ctrl->value);
		ret = fimc_is_itf_i2c_lock(device, I2C_L0, false);
		if (ret) {
			err("fimc_is_itf_i2c_unlock fail\n");
			break;
		}
		dbg_isp("V4L2_CID_IS_DVFS_LOCK : %d\n", ctrl->value);
		break;
	case V4L2_CID_IS_DVFS_UNLOCK:
		ret = fimc_is_itf_i2c_lock(device, i2c_clk, true);
		if (ret) {
			err("fimc_is_itf_i2_clock fail\n");
			break;
		}
		pm_qos_remove_request(&device->user_qos);
		ret = fimc_is_itf_i2c_lock(device, i2c_clk, false);
		if (ret) {
			err("fimc_is_itf_i2c_unlock fail\n");
			break;
		}
		dbg_isp("V4L2_CID_IS_DVFS_UNLOCK : %d I2C(%d)\n", ctrl->value, i2c_clk);
		break;
	case V4L2_CID_IS_SET_SETFILE:
		if (test_bit(FIMC_IS_SUBDEV_START, &device->group_isp.leader.state)) {
			err("Setting setfile is only avaiable before starting device!! (0x%08x)",
					ctrl->value);
			ret = -EINVAL;
		} else {
			device->setfile = ctrl->value;
			minfo("[ISP:V] setfile: 0x%08X\n", vctx, ctrl->value);
		}
		break;
	case V4L2_CID_IS_COLOR_RANGE:
		if (test_bit(FIMC_IS_SUBDEV_START, &device->group_isp.leader.state)) {
			err("failed to change color range: device started already (0x%08x)",
					ctrl->value);
			ret = -EINVAL;
		} else {
			device->color_range &= ~FIMC_IS_ISP_CRANGE_MASK;

			if (ctrl->value)
				device->color_range	|=
					(FIMC_IS_CRANGE_LIMITED << FIMC_IS_ISP_CRANGE_SHIFT);
		}
		break;
	case V4L2_CID_IS_MAP_BUFFER:
		{
			/* hack for 64bit addr */
			ulong value_to_addr;
			struct fimc_is_queue *queue;
			struct fimc_is_framemgr *framemgr;
			struct fimc_is_frame *frame;
			struct dma_buf *dmabuf;
			struct dma_buf_attachment *attachment;
			dma_addr_t dva;
			struct v4l2_buffer *buf;
			struct v4l2_plane *planes;
			size_t size;
			u32 write, plane, group_id;

			size = sizeof(struct v4l2_buffer);
			buf = kmalloc(size, GFP_KERNEL);
			if (!buf) {
				merr("kmalloc is fail", vctx);
				ret = -EINVAL;
				goto p_err;
			}
			/* hack for 64bit addr */
			value_to_addr = ctrl->value;

			ret = copy_from_user(buf, (void __user *)value_to_addr, size);
			if (ret) {
				merr("copy_from_user is fail(%d)", vctx, ret);
				kfree(buf);
				ret = -EINVAL;
				goto p_err;
			}

			if (!V4L2_TYPE_IS_MULTIPLANAR(buf->type)) {
				merr("single plane is not supported", vctx);
				kfree(buf);
				ret = -EINVAL;
				goto p_err;
			}

			if (buf->index >= FRAMEMGR_MAX_REQUEST) {
				merr("buffer index is invalid(%d)", vctx, buf->index);
				kfree(buf);
				ret = -EINVAL;
				goto p_err;
			}

			if (buf->length > VIDEO_MAX_PLANES) {
				merr("planes[%d] is invalid", vctx, buf->length);
				kfree(buf);
				ret = -EINVAL;
				goto p_err;
			}

			queue = GET_QUEUE(vctx, buf->type);
			if (queue->vbq->memory != V4L2_MEMORY_DMABUF) {
				merr("memory type(%d) is not supported", vctx, queue->vbq->memory);
				kfree(buf);
				ret = -EINVAL;
				goto p_err;
			}

			size = sizeof(struct v4l2_plane) * buf->length;
			planes = kmalloc(size, GFP_KERNEL);
			if (IS_ERR(planes)) {
				merr("kmalloc is fail(%p)", vctx, planes);
				kfree(buf);
				ret = -EINVAL;
				goto p_err;
			}

			ret = copy_from_user(planes, (void __user *)buf->m.planes, size);
			if (ret) {
				merr("copy_from_user is fail(%d)", vctx, ret);
				kfree(planes);
				kfree(buf);
				ret = -EINVAL;
				goto p_err;
			}

			framemgr = &queue->framemgr;
			frame = &framemgr->frame[buf->index];
			if (test_bit(FRAME_MAP_MEM, &frame->memory)) {
				merr("this buffer(%d) is already mapped", vctx, buf->index);
				kfree(planes);
				kfree(buf);
				ret = -EINVAL;
				goto p_err;
			}

			/* only last buffer need to map */
			if (buf->length >= 1) {
				plane = buf->length - 1;
			} else {
				merr("buffer length is not correct(%d)", vctx, buf->length);
				kfree(planes);
				kfree(buf);
				ret = -EINVAL;
				goto p_err;
			}

			dmabuf = dma_buf_get(planes[plane].m.fd);
			if (IS_ERR(dmabuf)) {
				merr("dma_buf_get is fail(%p)", vctx, dmabuf);
				kfree(planes);
				kfree(buf);
				ret = -EINVAL;
				goto p_err;
			}

			attachment = dma_buf_attach(dmabuf, &device->pdev->dev);
			if (IS_ERR(attachment)) {
				merr("dma_buf_attach is fail(%p)", vctx, attachment);
				kfree(planes);
				kfree(buf);
				dma_buf_put(dmabuf);
				ret = -EINVAL;
				goto p_err;
			}

			write = !V4L2_TYPE_IS_OUTPUT(buf->type);
			dva = ion_iovmm_map(attachment, 0, dmabuf->size, write, plane);
			if (IS_ERR_VALUE(dva)) {
				merr("ion_iovmm_map is fail(%pa)", vctx, &dva);
				kfree(planes);
				kfree(buf);
				dma_buf_detach(dmabuf, attachment);
				dma_buf_put(dmabuf);
				ret = -EINVAL;
				goto p_err;
			}

			group_id = GROUP_ID(device->group_isp.id);
			ret = fimc_is_itf_map(device, group_id, dva, dmabuf->size);
			if (ret) {
				merr("fimc_is_itf_map is fail(%d)", vctx, ret);
				kfree(planes);
				kfree(buf);
				dma_buf_detach(dmabuf, attachment);
				dma_buf_put(dmabuf);
				goto p_err;
			}

			minfo("[ISP:V] buffer%d.plane%d mapping\n", vctx, buf->index, plane);
			set_bit(FRAME_MAP_MEM, &frame->memory);
			dma_buf_detach(dmabuf, attachment);
			dma_buf_put(dmabuf);
			kfree(planes);
			kfree(buf);
		}
		break;
	default:
		err("unsupported ioctl(%d)\n", ctrl->id);
		ret = -EINVAL;
		break;
	}

p_err:
	return ret;
}
コード例 #2
0
int fimc_is_video_s_ctrl(struct file *file,
	struct fimc_is_video_ctx *vctx,
	struct v4l2_control *ctrl)
{
	int ret = 0;
	/* hack for 64bit addr */
	ulong value_to_addr = 0;
	struct fimc_is_video *video;
	struct fimc_is_device_ischain *device;
	struct fimc_is_resourcemgr *resourcemgr;

	BUG_ON(!vctx);
	BUG_ON(!GET_DEVICE(vctx));
	BUG_ON(!GET_VIDEO(vctx));
	BUG_ON(!ctrl);

	device = GET_DEVICE(vctx);
	video = GET_VIDEO(vctx);
	resourcemgr = device->resourcemgr;

	switch (ctrl->id) {
	case V4L2_CID_IS_END_OF_STREAM:
		ret = fimc_is_ischain_open_wrap(device, true);
		if (ret) {
			merr("fimc_is_ischain_open_wrap is fail(%d)", device, ret);
			goto p_err;
		}
		break;
	case V4L2_CID_IS_SET_SETFILE:
		if (test_bit(FIMC_IS_ISCHAIN_START, &device->state)) {
			merr("device is already started, setfile applying is fail", device);
			ret = -EINVAL;
			goto p_err;
		}

		device->setfile = ctrl->value;
		break;
	case V4L2_CID_IS_HAL_VERSION:
		if (ctrl->value < 0 || ctrl->value >= IS_HAL_VER_MAX) {
			merr("hal version(%d) is invalid", device, ctrl->value);
			ret = -EINVAL;
			goto p_err;
		}
		resourcemgr->hal_version = ctrl->value;
		break;
	case V4L2_CID_IS_DEBUG_DUMP:
		info("Print fimc-is info dump by HAL");
		fimc_is_hw_logdump(device->interface);
		fimc_is_hw_regdump(device->interface);
		CALL_POPS(device, print_clk);

		if (ctrl->value)
			panic("intentional panic from camera HAL");
		break;
	case V4L2_CID_IS_DVFS_CLUSTER0:
	case V4L2_CID_IS_DVFS_CLUSTER1:
		fimc_is_resource_ioctl(resourcemgr, ctrl);
		break;
	case V4L2_CID_IS_DEBUG_SYNC_LOG:
		fimc_is_logsync(device->interface, ctrl->value, IS_MSG_TEST_SYNC_LOG);
		break;
	case V4L2_CID_IS_MAP_BUFFER:
		{
			struct fimc_is_queue *queue;
			struct fimc_is_framemgr *framemgr;
			struct fimc_is_frame *frame;
			struct dma_buf *dmabuf;
			struct dma_buf_attachment *attachment;
			dma_addr_t dva;
			struct v4l2_buffer *buf;
			struct v4l2_plane *planes;
			size_t size;
			u32 plane, group_id;

			size = sizeof(struct v4l2_buffer);
			buf = kmalloc(size, GFP_KERNEL);
			if (!buf) {
				mverr("kmalloc is fail(%p)", device, video, buf);
				ret = -EINVAL;
				goto p_err;
			}
			/* hack for 64bit addr */
			value_to_addr = ctrl->value;

			ret = copy_from_user(buf, (void __user *)value_to_addr, size);
			if (ret) {
				mverr("copy_from_user is fail(%d)", device, video, ret);
				kfree(buf);
				ret = -EINVAL;
				goto p_err;
			}

			if (!V4L2_TYPE_IS_OUTPUT(buf->type)) {
				mverr("capture video type is not supported", device, video);
				kfree(buf);
				ret = -EINVAL;
				goto p_err;
			}

			if (!V4L2_TYPE_IS_MULTIPLANAR(buf->type)) {
				mverr("single plane is not supported", device, video);
				kfree(buf);
				ret = -EINVAL;
				goto p_err;
			}

			if (buf->index >= FRAMEMGR_MAX_REQUEST) {
				mverr("buffer index is invalid(%d)", device, video, buf->index);
				kfree(buf);
				ret = -EINVAL;
				goto p_err;
			}

			if (buf->length > VIDEO_MAX_PLANES) {
				mverr("planes[%d] is invalid", device, video, buf->length);
				kfree(buf);
				ret = -EINVAL;
				goto p_err;
			}

			queue = GET_QUEUE(vctx);
			if (queue->vbq->memory != V4L2_MEMORY_DMABUF) {
				mverr("memory type(%d) is not supported", device, video, queue->vbq->memory);
				kfree(buf);
				ret = -EINVAL;
				goto p_err;
			}

			size = sizeof(struct v4l2_plane) * buf->length;
			planes = kmalloc(size, GFP_KERNEL);
			if (!planes) {
				mverr("kmalloc is fail(%p)", device, video, planes);
				kfree(buf);
				ret = -EINVAL;
				goto p_err;
			}

			ret = copy_from_user(planes, (void __user *)buf->m.planes, size);
			if (ret) {
				mverr("copy_from_user is fail(%d)", device, video, ret);
				kfree(planes);
				kfree(buf);
				ret = -EINVAL;
				goto p_err;
			}

			framemgr = &queue->framemgr;
			frame = &framemgr->frame[buf->index];
			if (test_bit(FRAME_MAP_MEM, &frame->memory)) {
				mverr("this buffer(%d) is already mapped", device, video, buf->index);
				kfree(planes);
				kfree(buf);
				ret = -EINVAL;
				goto p_err;
			}

			/* only last buffer need to map */
			if (buf->length <= 1) {
				mverr("this buffer(%d) have no meta plane", device, video, buf->length);
				kfree(planes);
				kfree(buf);
				ret = -EINVAL;
				goto p_err;
			}

			plane = buf->length - 1;
			dmabuf = dma_buf_get(planes[plane].m.fd);
			if (IS_ERR(dmabuf)) {
				mverr("dma_buf_get is fail(%p)", device, video, dmabuf);
				kfree(planes);
				kfree(buf);
				ret = -EINVAL;
				goto p_err;
			}

			attachment = dma_buf_attach(dmabuf, &device->pdev->dev);
			if (IS_ERR(attachment)) {
				mverr("dma_buf_attach is fail(%p)", device, video, attachment);
				kfree(planes);
				kfree(buf);
				dma_buf_put(dmabuf);
				ret = -EINVAL;
				goto p_err;
			}

			/* only support output(read) video node */
			dva = ion_iovmm_map(attachment, 0, dmabuf->size, 0, plane);
			if (IS_ERR_VALUE(dva)) {
				mverr("ion_iovmm_map is fail(%pa)", device, video, &dva);
				kfree(planes);
				kfree(buf);
				dma_buf_detach(dmabuf, attachment);
				dma_buf_put(dmabuf);
				ret = -EINVAL;
				goto p_err;
			}

			group_id = GROUP_ID(device->group_3aa.id);
			ret = fimc_is_itf_map(device, group_id, dva, dmabuf->size);
			if (ret) {
				mverr("fimc_is_itf_map is fail(%d)", device, video, ret);
				kfree(planes);
				kfree(buf);
				dma_buf_detach(dmabuf, attachment);
				dma_buf_put(dmabuf);
				goto p_err;
			}

			mvinfo(" B%d.P%d MAP\n", device, video, buf->index, plane);
			set_bit(FRAME_MAP_MEM, &frame->memory);
			dma_buf_detach(dmabuf, attachment);
			dma_buf_put(dmabuf);
			kfree(planes);
			kfree(buf);
		}
		break;
	default:
		err("unsupported ioctl(0x%X)", ctrl->id);
		ret = -EINVAL;
		break;
	}

p_err:
	return ret;
}
コード例 #3
0
static void __fimc_is_fault_handler(struct device *dev)
{
	u32 i, j, k;
	struct fimc_is_core *core;
	struct fimc_is_device_sensor *sensor;
	struct fimc_is_device_ischain *ischain;
	struct fimc_is_subdev *subdev;
	struct fimc_is_framemgr *framemgr;
	struct fimc_is_resourcemgr *resourcemgr;

	core = dev_get_drvdata(dev);
	if (core) {
		resourcemgr = &core->resourcemgr;

		fimc_is_hw_fault(&core->interface);
		/* dump FW page table 1nd(~16KB), 2nd(16KB~32KB) */
		fimc_is_hw_memdump(&core->interface,
			resourcemgr->minfo.kvaddr + FIMC_IS_TTB_OFFSET, /* TTB_BASE ~ 32KB */
			resourcemgr->minfo.kvaddr + FIMC_IS_TTB_OFFSET + FIMC_IS_TTB_SIZE);
		fimc_is_hw_logdump(&core->interface);

		/* SENSOR */
		for (i = 0; i < FIMC_IS_SENSOR_COUNT; i++) {
			sensor = &core->sensor[i];
			framemgr = GET_FRAMEMGR(sensor->vctx);
			if (test_bit(FIMC_IS_SENSOR_OPEN, &sensor->state) && framemgr) {
				struct fimc_is_device_flite *flite;
				struct fimc_is_device_csi *csi;

				for (j = 0; j < framemgr->num_frames; ++j) {
					for (k = 0; k < framemgr->frames[j].planes; k++) {
						pr_err("[SS%d] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
							framemgr->frames[j].dvaddr_buffer[k],
							framemgr->frames[j].mem_state);
					}
				}

				/* vc0 */
				framemgr = GET_SUBDEV_FRAMEMGR(&sensor->ssvc0);
				if (test_bit(FIMC_IS_SUBDEV_START, &sensor->ssvc0.state) && framemgr) {
					for (j = 0; j < framemgr->num_frames; ++j) {
						for (k = 0; k < framemgr->frames[j].planes; k++) {
							pr_err("[SS%dVC0] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
									framemgr->frames[j].dvaddr_buffer[k],
									framemgr->frames[j].mem_state);
						}
					}
				}

				/* vc1 */
				framemgr = GET_SUBDEV_FRAMEMGR(&sensor->ssvc1);
				if (test_bit(FIMC_IS_SUBDEV_START, &sensor->ssvc1.state) && framemgr) {
					for (j = 0; j < framemgr->num_frames; ++j) {
						for (k = 0; k < framemgr->frames[j].planes; k++) {
							pr_err("[SS%dVC1] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
									framemgr->frames[j].dvaddr_buffer[k],
									framemgr->frames[j].mem_state);
						}
					}
				}

				/* vc2 */
				framemgr = GET_SUBDEV_FRAMEMGR(&sensor->ssvc2);
				if (test_bit(FIMC_IS_SUBDEV_START, &sensor->ssvc2.state) && framemgr) {
					for (j = 0; j < framemgr->num_frames; ++j) {
						for (k = 0; k < framemgr->frames[j].planes; k++) {
							pr_err("[SS%dVC2] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
									framemgr->frames[j].dvaddr_buffer[k],
									framemgr->frames[j].mem_state);
						}
					}
				}

				/* vc3 */
				framemgr = GET_SUBDEV_FRAMEMGR(&sensor->ssvc3);
				if (test_bit(FIMC_IS_SUBDEV_START, &sensor->ssvc3.state) && framemgr) {
					for (j = 0; j < framemgr->num_frames; ++j) {
						for (k = 0; k < framemgr->frames[j].planes; k++) {
							pr_err("[SS%dVC3] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
									framemgr->frames[j].dvaddr_buffer[k],
									framemgr->frames[j].mem_state);
						}
					}
				}

				/* csis, bns sfr dump */
				flite = (struct fimc_is_device_flite *)v4l2_get_subdevdata(sensor->subdev_flite);
				if (flite)
					flite_hw_dump(flite->base_reg);

				csi = (struct fimc_is_device_csi *)v4l2_get_subdevdata(sensor->subdev_csi);
				if (csi)
					csi_hw_dump(csi->base_reg);
			}
		}

		/* ISCHAIN */
		for (i = 0; i < FIMC_IS_STREAM_COUNT; i++) {
			ischain = &core->ischain[i];
			if (test_bit(FIMC_IS_ISCHAIN_OPEN, &ischain->state)) {
				/* 3AA */
				subdev = &ischain->group_3aa.leader;
				framemgr = GET_SUBDEV_FRAMEMGR(subdev);
				if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
					for (j = 0; j < framemgr->num_frames; ++j) {
						for (k = 0; k < framemgr->frames[j].planes; k++) {
							pr_err("[%d][3XS] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
								framemgr->frames[j].dvaddr_buffer[k],
								framemgr->frames[j].mem_state);
						}
					}
				}
				/* 3AAC */
				subdev = &ischain->txc;
				framemgr = GET_SUBDEV_FRAMEMGR(subdev);
				if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
					for (j = 0; j < framemgr->num_frames; ++j) {
						for (k = 0; k < framemgr->frames[j].planes; k++) {
							pr_err("[%d][3XC] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
								framemgr->frames[j].dvaddr_buffer[k],
								framemgr->frames[j].mem_state);
						}
					}
				}
				/* 3AAP */
				subdev = &ischain->txp;
				framemgr = GET_SUBDEV_FRAMEMGR(subdev);
				if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
					for (j = 0; j < framemgr->num_frames; ++j) {
						for (k = 0; k < framemgr->frames[j].planes; k++) {
							pr_err("[%d][3XP] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
								framemgr->frames[j].dvaddr_buffer[k],
								framemgr->frames[j].mem_state);
						}
					}
				}
				/* ISP */
				subdev = &ischain->group_isp.leader;
				framemgr = GET_SUBDEV_FRAMEMGR(subdev);
				if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
					for (j = 0; j < framemgr->num_frames; ++j) {
						for (k = 0; k < framemgr->frames[j].planes; k++) {
							pr_err("[%d][IXS] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
								framemgr->frames[j].dvaddr_buffer[k],
								framemgr->frames[j].mem_state);
						}
					}
				}
				/* ISPC */
				subdev = &ischain->ixc;
				framemgr = GET_SUBDEV_FRAMEMGR(subdev);
				if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
					for (j = 0; j < framemgr->num_frames; ++j) {
						for (k = 0; k < framemgr->frames[j].planes; k++) {
							pr_err("[%d][IXC] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
								framemgr->frames[j].dvaddr_buffer[k],
								framemgr->frames[j].mem_state);
						}
					}
				}
				/* ISPP */
				subdev = &ischain->ixp;
				framemgr = GET_SUBDEV_FRAMEMGR(subdev);
				if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
					for (j = 0; j < framemgr->num_frames; ++j) {
						for (k = 0; k < framemgr->frames[j].planes; k++) {
							pr_err("[%d][IXP] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
								framemgr->frames[j].dvaddr_buffer[k],
								framemgr->frames[j].mem_state);
						}
					}
				}
				/* DIS */
				subdev = &ischain->group_dis.leader;
				framemgr = GET_SUBDEV_FRAMEMGR(subdev);
				if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
					for (j = 0; j < framemgr->num_frames; ++j) {
						for (k = 0; k < framemgr->frames[j].planes; k++) {
							pr_err("[%d][DIS] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
								framemgr->frames[j].dvaddr_buffer[k],
								framemgr->frames[j].mem_state);
						}
					}
				}
				/* SCC */
				subdev = &ischain->scc;
				framemgr = GET_SUBDEV_FRAMEMGR(subdev);
				if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
					for (j = 0; j < framemgr->num_frames; ++j) {
						for (k = 0; k < framemgr->frames[j].planes; k++) {
							pr_err("[%d][SCC] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
								framemgr->frames[j].dvaddr_buffer[k],
								framemgr->frames[j].mem_state);
						}
					}
				}
				/* SCP */
				subdev = &ischain->scp;
				framemgr = GET_SUBDEV_FRAMEMGR(subdev);
				if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
					for (j = 0; j < framemgr->num_frames; ++j) {
						for (k = 0; k < framemgr->frames[j].planes; k++) {
							pr_err("[%d][SCP] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
								framemgr->frames[j].dvaddr_buffer[k],
								framemgr->frames[j].mem_state);
						}
					}
				}
				/* MCS */
				subdev = &ischain->group_mcs.leader;
				framemgr = GET_SUBDEV_FRAMEMGR(subdev);
				if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
					for (j = 0; j < framemgr->num_frames; ++j) {
						for (k = 0; k < framemgr->frames[j].planes; k++) {
							pr_err("[%d][MCS] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
								framemgr->frames[j].dvaddr_buffer[k],
								framemgr->frames[j].mem_state);
						}
					}
				}
				/* M0P */
				subdev = &ischain->m0p;
				framemgr = GET_SUBDEV_FRAMEMGR(subdev);
				if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
					for (j = 0; j < framemgr->num_frames; ++j) {
						for (k = 0; k < framemgr->frames[j].planes; k++) {
							pr_err("[%d][M0P] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
								framemgr->frames[j].dvaddr_buffer[k],
								framemgr->frames[j].mem_state);
						}
					}
				}
				/* M1P */
				subdev = &ischain->m1p;
				framemgr = GET_SUBDEV_FRAMEMGR(subdev);
				if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
					for (j = 0; j < framemgr->num_frames; ++j) {
						for (k = 0; k < framemgr->frames[j].planes; k++) {
							pr_err("[%d][M1P] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
								framemgr->frames[j].dvaddr_buffer[k],
								framemgr->frames[j].mem_state);
						}
					}
				}
				/* M2P */
				subdev = &ischain->m2p;
				framemgr = GET_SUBDEV_FRAMEMGR(subdev);
				if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
					for (j = 0; j < framemgr->num_frames; ++j) {
						for (k = 0; k < framemgr->frames[j].planes; k++) {
							pr_err("[%d][M2P] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
								framemgr->frames[j].dvaddr_buffer[k],
								framemgr->frames[j].mem_state);
						}
					}
				}
				/* M3P */
				subdev = &ischain->m3p;
				framemgr = GET_SUBDEV_FRAMEMGR(subdev);
				if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
					for (j = 0; j < framemgr->num_frames; ++j) {
						for (k = 0; k < framemgr->frames[j].planes; k++) {
							pr_err("[%d][M3P] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
								framemgr->frames[j].dvaddr_buffer[k],
								framemgr->frames[j].mem_state);
						}
					}
				}
				/* M4P */
				subdev = &ischain->m4p;
				framemgr = GET_SUBDEV_FRAMEMGR(subdev);
				if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
					for (j = 0; j < framemgr->num_frames; ++j) {
						for (k = 0; k < framemgr->frames[j].planes; k++) {
							pr_err("[%d][M4P] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
								framemgr->frames[j].dvaddr_buffer[k],
								framemgr->frames[j].mem_state);
						}
					}
				}
				/* VRA */
				subdev = &ischain->group_vra.leader;
				framemgr = GET_SUBDEV_FRAMEMGR(subdev);
				if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
					for (j = 0; j < framemgr->num_frames; ++j) {
						for (k = 0; k < framemgr->frames[j].planes; k++) {
							pr_err("[%d][VRA] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
								framemgr->frames[j].dvaddr_buffer[k],
								framemgr->frames[j].mem_state);
						}
					}
				}
			}
		}
	} else {
		pr_err("failed to get core\n");
	}
}