static int fimc_is_hw_open_sensor(struct fimc_is *is,
struct fimc_is_sensor *sensor)
{
struct sensor_open_extended *soe = (void *)&is->is_p_region->shared;
fimc_is_hw_wait_intmsr0_intmsd0(is);
soe->self_calibration_mode = 1;
soe->actuator_type = 0;
soe->mipi_lane_num = 0;
soe->mclk = 0;
soe->mipi_speed = 0;
soe->fast_open_sensor = 0;
soe->i2c_sclk = 88000000;
fimc_is_mem_barrier();
mcuctl_write(HIC_OPEN_SENSOR, is, MCUCTL_REG_ISSR(0));
mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
mcuctl_write(sensor->drvdata->id, is, MCUCTL_REG_ISSR(2));
mcuctl_write(sensor->i2c_bus, is, MCUCTL_REG_ISSR(3));
mcuctl_write(is->is_dma_p_region, is, MCUCTL_REG_ISSR(4));
fimc_is_hw_set_intgr0_gd0(is);
return fimc_is_wait_event(is, IS_ST_OPEN_SENSOR, 1,
FIMC_IS_SENSOR_OPEN_TIMEOUT);
}
static int isp_video_s_fmt_mplane(struct file *file, void *priv,
struct v4l2_format *f)
{
struct fimc_isp *isp = video_drvdata(file);
struct fimc_is *is = fimc_isp_to_is(isp);
struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
const struct fimc_fmt *ifmt = NULL;
struct param_dma_output *dma = __get_isp_dma2(is);
__isp_video_try_fmt(isp, pixm, &ifmt);
if (WARN_ON(ifmt == NULL))
return -EINVAL;
dma->format = DMA_OUTPUT_FORMAT_BAYER;
dma->order = DMA_OUTPUT_ORDER_GB_BG;
dma->plane = ifmt->memplanes;
dma->bitwidth = ifmt->depth[0];
dma->width = pixm->width;
dma->height = pixm->height;
fimc_is_mem_barrier();
isp->video_capture.format = ifmt;
isp->video_capture.pixfmt = *pixm;
return 0;
}
static void fimc_is_load_firmware(const struct firmware *fw, void *context)
{
struct fimc_is *is = context;
struct device *dev = &is->pdev->dev;
void *buf;
int ret;
if (fw == NULL) {
dev_err(dev, "firmware request failed\n");
return;
}
mutex_lock(&is->lock);
if (fw->size < FIMC_IS_FW_SIZE_MIN || fw->size > FIMC_IS_FW_SIZE_MAX) {
dev_err(dev, "wrong firmware size: %d\n", fw->size);
goto done;
}
is->fw.size = fw->size;
ret = fimc_is_alloc_cpu_memory(is);
if (ret < 0) {
dev_err(dev, "failed to allocate FIMC-IS CPU memory\n");
goto done;
}
memcpy(is->memory.vaddr, fw->data, fw->size);
wmb();
/* Read firmware description. */
buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_DESC_LEN);
memcpy(&is->fw.info, buf, FIMC_IS_FW_INFO_LEN);
is->fw.info[FIMC_IS_FW_INFO_LEN] = 0;
buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_VER_LEN);
memcpy(&is->fw.version, buf, FIMC_IS_FW_VER_LEN);
is->fw.version[FIMC_IS_FW_VER_LEN - 1] = 0;
is->fw.state = 1;
dev_info(dev, "loaded firmware: %s, rev. %s\n",
is->fw.info, is->fw.version);
dev_dbg(dev, "FW size: %d, paddr: %#x\n", fw->size, is->memory.paddr);
is->is_shared_region->chip_id = 0xe4412;
is->is_shared_region->chip_rev_no = 1;
fimc_is_mem_barrier();
/*
* FIXME: The firmware is not being released for now, as it is
* needed around for copying to the IS working memory every
* time before the Cortex-A5 is restarted.
*/
if (is->fw.f_w)
release_firmware(is->fw.f_w);
is->fw.f_w = fw;
done:
mutex_unlock(&is->lock);
}
static int fimc_is_load_setfile(struct fimc_is *is, char *file_name)
{
const struct firmware *fw;
void *buf;
int ret;
ret = request_firmware(&fw, file_name, &is->pdev->dev);
if (ret < 0) {
dev_err(&is->pdev->dev, "firmware request failed (%d)\n", ret);
return ret;
}
buf = is->memory.vaddr + is->setfile.base;
memcpy(buf, fw->data, fw->size);
fimc_is_mem_barrier();
is->setfile.size = fw->size;
pr_debug("mem vaddr: %p, setfile buf: %p\n", is->memory.vaddr, buf);
memcpy(is->fw.setfile_info,
fw->data + fw->size - FIMC_IS_SETFILE_INFO_LEN,
FIMC_IS_SETFILE_INFO_LEN - 1);
is->fw.setfile_info[FIMC_IS_SETFILE_INFO_LEN - 1] = '\0';
is->setfile.state = 1;
pr_debug("FIMC-IS setfile loaded: base: %#x, size: %zu B\n",
is->setfile.base, fw->size);
release_firmware(fw);
return ret;
}
static int fimc_isp_subdev_s_stream(struct v4l2_subdev *sd, int on)
{
struct fimc_isp *isp = v4l2_get_subdevdata(sd);
struct fimc_is *is = fimc_isp_to_is(isp);
int ret;
isp_dbg(1, sd, "%s: on: %d\n", __func__, on);
if (!test_bit(IS_ST_INIT_DONE, &is->state))
return -EBUSY;
fimc_is_mem_barrier();
if (on) {
if (__get_pending_param_count(is)) {
ret = fimc_is_itf_s_param(is, true);
if (ret < 0)
return ret;
}
isp_dbg(1, sd, "changing mode to %d\n", is->config_index);
ret = fimc_is_itf_mode_change(is);
if (ret)
return -EINVAL;
clear_bit(IS_ST_STREAM_ON, &is->state);
fimc_is_hw_stream_on(is);
ret = fimc_is_wait_event(is, IS_ST_STREAM_ON, 1,
FIMC_IS_CONFIG_TIMEOUT);
if (ret < 0) {
v4l2_err(sd, "stream on timeout\n");
return ret;
}
} else {
clear_bit(IS_ST_STREAM_OFF, &is->state);
fimc_is_hw_stream_off(is);
ret = fimc_is_wait_event(is, IS_ST_STREAM_OFF, 1,
FIMC_IS_CONFIG_TIMEOUT);
if (ret < 0) {
v4l2_err(sd, "stream off timeout\n");
return ret;
}
is->setfile.sub_index = 0;
}
return 0;
}
int fimc_is_itf_s_param(struct fimc_is *is, bool update)
{
int ret;
if (update)
__is_hw_update_params(is);
fimc_is_mem_barrier();
clear_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
fimc_is_hw_set_param(is);
ret = fimc_is_wait_event(is, IS_ST_BLOCK_CMD_CLEARED, 1,
FIMC_IS_CONFIG_TIMEOUT);
if (ret < 0)
dev_err(&is->pdev->dev, "%s() timeout\n", __func__);
return ret;
}
static int isp_video_capture_start_streaming(struct vb2_queue *q,
unsigned int count)
{
struct fimc_isp *isp = vb2_get_drv_priv(q);
struct fimc_is *is = fimc_isp_to_is(isp);
struct param_dma_output *dma = __get_isp_dma2(is);
struct fimc_is_video *video = &isp->video_capture;
int ret;
if (!test_bit(ST_ISP_VID_CAP_BUF_PREP, &isp->state) ||
test_bit(ST_ISP_VID_CAP_STREAMING, &isp->state))
return 0;
dma->cmd = DMA_OUTPUT_COMMAND_ENABLE;
dma->notify_dma_done = DMA_OUTPUT_NOTIFY_DMA_DONE_ENABLE;
dma->buffer_address = is->is_dma_p_region +
DMA2_OUTPUT_ADDR_ARRAY_OFFS;
dma->buffer_number = video->reqbufs_count;
dma->dma_out_mask = video->buf_mask;
isp_dbg(2, &video->ve.vdev,
"buf_count: %d, planes: %d, dma addr table: %#x\n",
video->buf_count, video->format->memplanes,
dma->buffer_address);
fimc_is_mem_barrier();
fimc_is_set_param_bit(is, PARAM_ISP_DMA2_OUTPUT);
__fimc_is_hw_update_param(is, PARAM_ISP_DMA2_OUTPUT);
ret = fimc_is_itf_s_param(is, false);
if (ret < 0)
return ret;
ret = fimc_pipeline_call(&video->ve, set_stream, 1);
if (ret < 0)
return ret;
set_bit(ST_ISP_VID_CAP_STREAMING, &isp->state);
return ret;
}
/* General IS interrupt handler */
static void fimc_is_general_irq_handler(struct fimc_is *is)
{
is->i2h_cmd.cmd = mcuctl_read(is, MCUCTL_REG_ISSR(10));
switch (is->i2h_cmd.cmd) {
case IHC_GET_SENSOR_NUM:
fimc_is_hw_get_params(is, 1);
fimc_is_hw_wait_intmsr0_intmsd0(is);
fimc_is_hw_set_sensor_num(is);
pr_debug("ISP FW version: %#x\n", is->i2h_cmd.args[0]);
break;
case IHC_SET_FACE_MARK:
case IHC_FRAME_DONE:
fimc_is_hw_get_params(is, 2);
break;
case IHC_SET_SHOT_MARK:
case IHC_AA_DONE:
case IH_REPLY_DONE:
fimc_is_hw_get_params(is, 3);
break;
case IH_REPLY_NOT_DONE:
fimc_is_hw_get_params(is, 4);
break;
case IHC_NOT_READY:
break;
default:
pr_info("unknown command: %#x\n", is->i2h_cmd.cmd);
}
fimc_is_fw_clear_irq1(is, FIMC_IS_INT_GENERAL);
switch (is->i2h_cmd.cmd) {
case IHC_GET_SENSOR_NUM:
fimc_is_hw_set_intgr0_gd0(is);
set_bit(IS_ST_A5_PWR_ON, &is->state);
break;
case IHC_SET_SHOT_MARK:
break;
case IHC_SET_FACE_MARK:
is->fd_header.count = is->i2h_cmd.args[0];
is->fd_header.index = is->i2h_cmd.args[1];
is->fd_header.offset = 0;
break;
case IHC_FRAME_DONE:
break;
case IHC_AA_DONE:
pr_debug("AA_DONE - %d, %d, %d\n", is->i2h_cmd.args[0],
is->i2h_cmd.args[1], is->i2h_cmd.args[2]);
break;
case IH_REPLY_DONE:
pr_debug("ISR_DONE: args[0]: %#x\n", is->i2h_cmd.args[0]);
switch (is->i2h_cmd.args[0]) {
case HIC_PREVIEW_STILL...HIC_CAPTURE_VIDEO:
/* Get CAC margin */
set_bit(IS_ST_CHANGE_MODE, &is->state);
is->isp.cac_margin_x = is->i2h_cmd.args[1];
is->isp.cac_margin_y = is->i2h_cmd.args[2];
pr_debug("CAC margin (x,y): (%d,%d)\n",
is->isp.cac_margin_x, is->isp.cac_margin_y);
break;
case HIC_STREAM_ON:
clear_bit(IS_ST_STREAM_OFF, &is->state);
set_bit(IS_ST_STREAM_ON, &is->state);
break;
case HIC_STREAM_OFF:
clear_bit(IS_ST_STREAM_ON, &is->state);
set_bit(IS_ST_STREAM_OFF, &is->state);
break;
case HIC_SET_PARAMETER:
is->config[is->config_index].p_region_index1 = 0;
is->config[is->config_index].p_region_index2 = 0;
set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
pr_debug("HIC_SET_PARAMETER\n");
break;
case HIC_GET_PARAMETER:
break;
case HIC_SET_TUNE:
break;
case HIC_GET_STATUS:
break;
case HIC_OPEN_SENSOR:
set_bit(IS_ST_OPEN_SENSOR, &is->state);
pr_debug("data lanes: %d, settle line: %d\n",
is->i2h_cmd.args[2], is->i2h_cmd.args[1]);
break;
case HIC_CLOSE_SENSOR:
clear_bit(IS_ST_OPEN_SENSOR, &is->state);
is->sensor_index = 0;
break;
case HIC_MSG_TEST:
pr_debug("config MSG level completed\n");
break;
case HIC_POWER_DOWN:
clear_bit(IS_ST_PWR_SUBIP_ON, &is->state);
break;
case HIC_GET_SET_FILE_ADDR:
is->setfile.base = is->i2h_cmd.args[1];
set_bit(IS_ST_SETFILE_LOADED, &is->state);
break;
case HIC_LOAD_SET_FILE:
set_bit(IS_ST_SETFILE_LOADED, &is->state);
break;
}
break;
case IH_REPLY_NOT_DONE:
pr_err("ISR_NDONE: %d: %#x, %s\n", is->i2h_cmd.args[0],
is->i2h_cmd.args[1],
fimc_is_strerr(is->i2h_cmd.args[1]));
if (is->i2h_cmd.args[1] & IS_ERROR_TIME_OUT_FLAG)
pr_err("IS_ERROR_TIME_OUT\n");
switch (is->i2h_cmd.args[1]) {
case IS_ERROR_SET_PARAMETER:
fimc_is_mem_barrier();
}
switch (is->i2h_cmd.args[0]) {
case HIC_SET_PARAMETER:
is->config[is->config_index].p_region_index1 = 0;
is->config[is->config_index].p_region_index2 = 0;
set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
break;
}
break;
case IHC_NOT_READY:
pr_err("IS control sequence error: Not Ready\n");
break;
}
wake_up(&is->irq_queue);
}
