static void __init cell_setup_arch(void)
{
#ifdef CONFIG_SPU_BASE
spu_priv1_ops = &spu_priv1_mmio_ops;
spu_management_ops = &spu_management_of_ops;
#endif
cbe_regs_init();
cell_set_dabrx();
#ifdef CONFIG_CBE_RAS
cbe_ras_init();
#endif
#ifdef CONFIG_SMP
smp_init_cell();
#endif
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000;
/* Find and initialize PCI host bridges */
init_pci_config_tokens();
find_and_init_phbs();
cbe_pervasive_init();
#ifdef CONFIG_DUMMY_CONSOLE
conswitchp = &dummy_con;
#endif
mmio_nvram_init();
}
static void __init cell_setup_arch(void)
{
#ifdef CONFIG_SPU_BASE
spu_priv1_ops = &spu_priv1_mmio_ops;
#endif
cbe_regs_init();
#ifdef CONFIG_CBE_RAS
cbe_ras_init();
#endif
#ifdef CONFIG_SMP
smp_init_cell();
#endif
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000;
if (ROOT_DEV == 0) {
printk("No ramdisk, default root is /dev/hda2\n");
ROOT_DEV = Root_HDA2;
}
/* Find and initialize PCI host bridges */
init_pci_config_tokens();
find_and_init_phbs();
cbe_pervasive_init();
#ifdef CONFIG_DUMMY_CONSOLE
conswitchp = &dummy_con;
#endif
mmio_nvram_init();
}
/***********************************************************************
* ppc64_pcibios_init
*
* Chance to initialize and structures or variable before PCI Bus walk.
*
*<4>buswalk [swapper : iSeries_pcibios_init Entry.
*<4>buswalk [swapper : IoMmTable Initialized 0xC00000000034BD30
*<4>buswalk [swapper : find_and_init_phbs Entry
*<4>buswalk [swapper : Create iSeries pci_controller:(0xC00000001F5C7000), Bus 0x0017
*<4>buswalk [swapper : Connect EADs: 0x17.00.12 = 0x00
*<4>buswalk [swapper : iSeries_assign_IRQ 0x0017.00.12 = 0x0091
*<4>buswalk [swapper : - allocate and assign IRQ 0x17.00.12 = 0x91
*<4>buswalk [swapper : - FoundDevice: 0x17.28.10 = 0x12AE
*<4>buswalk [swapper : - build_device_node 0x17.28.12
*<4>buswalk [swapper : iSeries_pcibios_init Exit.
***********************************************************************/
void iSeries_pcibios_init(void)
{
PPCDBG(PPCDBG_BUSWALK,"iSeries_pcibios_init Entry.\n");
iSeries_IoMmTable_Initialize();
find_and_init_phbs();
pci_assign_all_busses = 0;
PPCDBG(PPCDBG_BUSWALK,"iSeries_pcibios_init Exit.\n");
}
static void __init pSeries_setup_arch(void)
{
/* Discover PIC type and setup ppc_md accordingly */
pseries_discover_pic();
/* openpic global configuration register (64-bit format). */
/* openpic Interrupt Source Unit pointer (64-bit format). */
/* python0 facility area (mmio) (64-bit format) REAL address. */
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000;
if (ROOT_DEV == 0) {
printk("No ramdisk, default root is /dev/sda2\n");
ROOT_DEV = Root_SDA2;
}
fwnmi_init();
/* Find and initialize PCI host bridges */
init_pci_config_tokens();
find_and_init_phbs();
eeh_init();
pSeries_nvram_init();
/* Choose an idle loop */
if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
vpa_init(boot_cpuid);
if (get_lppaca()->shared_proc) {
printk(KERN_DEBUG "Using shared processor idle loop\n");
ppc_md.power_save = pseries_shared_idle_sleep;
} else {
printk(KERN_DEBUG "Using dedicated idle loop\n");
ppc_md.power_save = pseries_dedicated_idle_sleep;
}
} else {
printk(KERN_DEBUG "Using default idle loop\n");
}
if (firmware_has_feature(FW_FEATURE_LPAR))
ppc_md.enable_pmcs = pseries_lpar_enable_pmcs;
else
ppc_md.enable_pmcs = power4_enable_pmcs;
}
static void __init cell_find_and_init_phbs(void)
{
struct device_node *axon, *plb5, *plb4, *np;
int index = 0;
/* Old blades, use generic code */
axon = of_find_node_by_name(NULL, "axon");
if (axon == NULL) {
find_and_init_phbs();
return;
}
/* New blades, manually instanciate bridges for now as
* RHEL5 doesn't have the infrastructure to do it from
* of_platform
*/
for (; axon; axon = of_find_node_by_name(axon, "axon")) {
for (plb5 = NULL; !!(plb5 = of_get_next_child(axon, plb5));)
if (strcmp(plb5->name, "plb5") == 0)
break;
if (plb5 == NULL)
continue;
for (np = NULL; !!(np = of_get_next_child(plb5, np));)
if ((strcmp(np->name, "pcie") == 0) ||
(strcmp(np->name, "pciex") == 0))
cell_add_phb(np, index++);
for (plb4 = NULL; !!(plb4 = of_get_next_child(plb5, plb4));)
if (strcmp(plb4->name, "plb4") == 0)
break;
of_node_put(plb5);
if (plb4 == NULL)
continue;
for (np = NULL; !!(np = of_get_next_child(plb4, np));)
if (strcmp(np->name, "pcix") == 0)
cell_add_phb(np, index++);
of_node_put(plb4);
}
pci_devs_phb_init();
}
static void __init pSeries_setup_arch(void)
{
/* Fixup ppc_md depending on the type of interrupt controller */
if (ppc64_interrupt_controller == IC_OPEN_PIC) {
ppc_md.init_IRQ = pSeries_init_mpic;
ppc_md.get_irq = mpic_get_irq;
ppc_md.cpu_irq_down = mpic_teardown_this_cpu;
/* Allocate the mpic now, so that find_and_init_phbs() can
* fill the ISUs */
pSeries_setup_mpic();
} else {
ppc_md.init_IRQ = xics_init_IRQ;
ppc_md.get_irq = xics_get_irq;
ppc_md.cpu_irq_down = xics_teardown_cpu;
}
#ifdef CONFIG_SMP
smp_init_pSeries();
#endif
/* openpic global configuration register (64-bit format). */
/* openpic Interrupt Source Unit pointer (64-bit format). */
/* python0 facility area (mmio) (64-bit format) REAL address. */
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000;
if (ROOT_DEV == 0) {
printk("No ramdisk, default root is /dev/sda2\n");
ROOT_DEV = Root_SDA2;
}
fwnmi_init();
/* Find and initialize PCI host bridges */
init_pci_config_tokens();
eeh_init();
find_and_init_phbs();
#ifdef CONFIG_DUMMY_CONSOLE
conswitchp = &dummy_con;
#endif
pSeries_nvram_init();
if (cur_cpu_spec->firmware_features & FW_FEATURE_SPLPAR)
vpa_init(boot_cpuid);
/* Choose an idle loop */
if (cur_cpu_spec->firmware_features & FW_FEATURE_SPLPAR) {
if (get_paca()->lppaca.shared_proc) {
printk(KERN_INFO "Using shared processor idle loop\n");
ppc_md.idle_loop = pseries_shared_idle;
} else {
printk(KERN_INFO "Using dedicated idle loop\n");
ppc_md.idle_loop = pseries_dedicated_idle;
}
} else {
printk(KERN_INFO "Using default idle loop\n");
ppc_md.idle_loop = default_idle;
}
}
