/*************************************************************************** * exit_zion_dmaif **************************************************************************/ void exit_zion_dmaif(void) { zion_params_t *zion_params; PINFO("Cleanup ZION DMAIF module ..."); /* get ZION parameters */ zion_params = find_zion (0); if (zion_params == NULL) { return; } /* Check Fireball */ if((zion_params->revision & 0xF000) == 0xF000) { return; } /* Disable backend interrupts */ mbus_writew(0, MBUS_ADDR(zion_params, ZION_MBUS_INTGEN_B)); /* INT Gen B Enable */ zion_disable_mbus_interrupt(zion_params, Dmaif_Int); mbus_writew(0, MBUS_ADDR(zion_params, ZION_MBUS_IOSEL)); /* DMA select */ free_zion_dmaif_private_space(ZION_DMAIF_PARAM (zion_params)); PINFO( "done.\n" ); return; }
static int zionvga_image_reflection(int frame) { u16 reg; zion_params_t *params = find_zion(0); if(params == NULL){ return -ENODEV; } reg = mbus_readw(MBUS_ADDR(params,ZIONVGA_VGA_SETTING)); if(frame==0) { reg &= ~(VGA_SEL); } else { reg |= VGA_SEL; } //reg |= (VGA_RSTR_EN|CSC_EN|TRS_ON); #if defined(CONFIG_P2PF_K240) || defined(CONFIG_P2PF_K202) || defined(CONFIG_P2PF_K246A) reg |= (CSC_EN); #else reg |= (CSC_EN|TRS_ON); //VGA_RSTR_EN is supporsed to be set by TX #endif //CONFIG_P2PF_K240 || CONFIG_P2PF_K246A mbus_writew(reg, MBUS_ADDR(params,ZIONVGA_VGA_SETTING)); //Just for assurance reg = mbus_readw(MBUS_ADDR(params,ZIONVGA_VGA_SETTING)); return 0; }
int zion_common_init(void) { zion_params_t *zion_params; struct proc_dir_entry *pentry; zion_params = find_zion(0); if(zion_params==NULL) { PERROR("ZION : not found\n"); return -ENODEV; } zion_params->zion_operations[ZION_COMMON]=&zion_common_fops; /* Make proc Entry */ pentry = create_proc_entry("zion/pcicreg",0,0); if(pentry) { pentry->read_proc = zion_proc_read; } if(1) { u16 revision = mbus_readw(MBUS_ADDR(zion_params,0)); zion_params->revision = revision; PINFO("ZION detected (Rev. %04X):\n" " Driver(Common Part): Version %s.%s.%s\n", revision, ZIONDRV_MAJOR_VER, ZIONDRV_MINOR_VER, ZIONDRV_PATCH_LEV); } return 0; }
int init_zion_audio_proc(void) { zion_params_t *zion_params; int ret; /* get ZION parameters */ zion_params = find_zion(0); if(zion_params == NULL) { return -ENODEV; } /* Check Fireball */ if((zion_params->revision & 0xF000) == 0xF000) { PINFO("This is fireball! ZION AudioProc cannot be used!!\n"); return 0; } /* register fuctions for operation */ zion_params->zion_operations[ZION_AUDIO_PROC]=&zion_audio_proc_fops; /* enable interruption */ ret = zion_enable_mbus_interrupt(zion_params, AudioProc_Int, zion_audio_proc_event); if(ret) { PERROR("registering interruption failed.\n"); return -EINVAL; } PINFO("ZION Audio Proc module Installed.\n"); return 0; }
/*************************************************************************** * init_zion_dmaif **************************************************************************/ int init_zion_dmaif(void) { zion_params_t *zion_params; int ret, i; /* get ZION parameters */ zion_params = find_zion(0); if (zion_params == NULL) { return -ENODEV; } /* Check Fireball */ if((zion_params->revision & 0xF000) == 0xF000) { PINFO("This is fireball! ZION DMA IF cannot be used!!\n"); return 0; } /* register fuctions for operation */ for (i = 0; i < ZION_EDMA_PORT; i++) { zion_params->zion_operations[ZION_DMAIF + i] = &zion_dmaif_port_fops; } /* Set Private Data Area */ zion_params->zion_private[ZION_DMAIF] = kmalloc(sizeof(zion_dmaif_params_t), GFP_KERNEL); if (ZION_DMAIF_PARAM(zion_params) == NULL) { PERROR ("Can't get enough space for private data.\n"); return -ENOMEM; } initialize_zion_dmaif_private_space(ZION_DMAIF_PARAM (zion_params)); #ifndef NEO_DEBUG PINFO("ZION DMAIF(EDMA) module ver. %d.%d Installed.\n", DMAIF_MAJORVER, DMAIF_MINORVER); #else /* NEO_DEBUG */ PINFO("ZION DMAIF(EDMA) module ver. %d.%d-DEBUG Installed.\n", DMAIF_MAJORVER, DMAIF_MINORVER); #endif /* !NEO_DEBUG */ /* enable interruption */ mbus_writew(ZION_MBUS_DMASEL_ENB, MBUS_ADDR(zion_params, ZION_MBUS_IOSEL)); /* DMA select */ ret = zion_enable_mbus_interrupt(zion_params, Dmaif_Int, zion_dmaif_event); if (ret) { PERROR ("registering interruption failed.\n"); return -EINVAL; } mbus_writew(ZION_MBUS_INTGB_MPU1ENB, MBUS_ADDR(zion_params, ZION_MBUS_INTGEN_B)); /* INT Gen B Enable */ return 0; }
static int zionvga_rstr_enable(void) { u16 reg; zion_params_t *params = find_zion(0); if(params == NULL){ return -ENODEV; } reg = mbus_readw(MBUS_ADDR(params,ZIONVGA_VGA_SETTING)); reg |= VGA_RSTR_EN; mbus_writew(reg, MBUS_ADDR(params,ZIONVGA_VGA_SETTING)); reg = mbus_readw(MBUS_ADDR(params,ZIONVGA_VGA_SETTING)); //Just for assurance return 0; }
/* * Cleanup */ void exit_zion_vga(void) { zion_params_t *params = find_zion(0); //Check Fireball if((params->revision & 0xF000) == 0xF000){ return; } /* * If your driver supports multiple boards, you should unregister and * clean up all instances. */ unregister_framebuffer(&zion_fb_info.fb_info); free_pages(zion_fb_info.ram_address, ZIONVGA_VRAM_ORDER); fb_dealloc_cmap(&zion_fb_info.fb_info.cmap); PINFO("ZION VGA cleanup\n"); }
void exit_zion_audio_proc(void) { zion_params_t *zion_params; /* get ZION parameters */ zion_params = find_zion(0); if(zion_params == NULL) { return; } /* Check Fireball */ if((zion_params->revision & 0xF000) == 0xF000) { return; } zion_disable_mbus_interrupt(zion_params, AudioProc_Int); return; }
static int zionvga_init_phase(struct zionvga_phase_arg *phase) { zion_params_t *params = find_zion(0); unsigned short v_phase = phase->v_phase; unsigned short h_phase = phase->h_phase; if(params == NULL){ return -ENODEV; } mbus_writew(v_phase, MBUS_ADDR(params, ZIONVGA_VIDEO_V_PHASE)); mbus_writew(v_phase, MBUS_ADDR(params, ZIONVGA_SYSTEM_V_PHASE)); mbus_writew(h_phase, MBUS_ADDR(params, ZIONVGA_VIDEO_H_PHASE)); mbus_writew(h_phase, MBUS_ADDR(params, ZIONVGA_SYSTEM_H_PHASE)); // Just for Assurance v_phase = mbus_readw(MBUS_ADDR(params, ZIONVGA_VIDEO_V_PHASE)); v_phase = mbus_readw(MBUS_ADDR(params, ZIONVGA_SYSTEM_V_PHASE)); h_phase = mbus_readw(MBUS_ADDR(params, ZIONVGA_VIDEO_H_PHASE)); h_phase = mbus_readw(MBUS_ADDR(params, ZIONVGA_SYSTEM_H_PHASE)); return 0; }
int init_zion_vga(void) { int ret; zion_params_t *params = find_zion(0); u32 off_addr; if(params == NULL){ return -ENODEV; } PINFO("ZION VGA Frame Buffer Driver Installed.\n"); PDEBUG("compiled "__DATE__" "__TIME__"\n"); //Check Fireball if((params->revision & 0xF000) == 0xF000){ PINFO("This is fireball! ZION VGA cannot be used!!\n"); return 0; } #ifdef CONFIG_ZION_FB_SETUP PINFO("Setting FB Address ... %p and %p\n", (void *)CONFIG_ZION_FB_FIRST_ADDR, (void *)CONFIG_ZION_FB_SECOND_ADDR); mbus_writel(CONFIG_ZION_FB_FIRST_ADDR, MBUS_ADDR(params,ZIONVGA_BUFFER_BASE_ADDRESS_0)); mbus_writel(CONFIG_ZION_FB_SECOND_ADDR, MBUS_ADDR(params,ZIONVGA_BUFFER_BASE_ADDRESS_1)); #endif //CONFIG_ZION_FB_SETUP //Get VGA FB Region off_addr = mbus_readl(MBUS_ADDR(params, ZIONVGA_BUFFER_BASE_ADDRESS_0)); dma_direction[0] = params->whole_sdram_addr + off_addr; PINFO("FB1_BUS_ADDR:%p\n",(void *)dma_direction[0]); off_addr = mbus_readl(MBUS_ADDR(params, ZIONVGA_BUFFER_BASE_ADDRESS_1)); dma_direction[1] = params->whole_sdram_addr + off_addr; PINFO("FB2_BUS_ADDR:%p\n",(void *)dma_direction[1]); memset(&zion_fb_info, 0, sizeof(struct zion_vga_info)); zion_fb_info.ram_address = (unsigned long)__get_free_pages(GFP_KERNEL | __GFP_DMA, ZIONVGA_VRAM_ORDER); if(!zion_fb_info.ram_address){ PERROR("failed get_free_pages(): ram_address\n"); ret = -ENOMEM; goto fail_gfp_fb; } memset((void *)zion_fb_info.ram_address, 0, ZIONVGA_VRAM_SIZE); PDEBUG("ram_address = 0x%08lx (virtual)\n", (unsigned long)zion_fb_info.ram_address); PDEBUG("ram_address = 0x%08lx (physical)\n", virt_to_bus((void *)zion_fb_info.ram_address)); zion_fb_info.fb_info.screen_base = (void __iomem *)zion_fb_info.ram_address; zion_fb_info.fb_info.fbops = &zion_vga_ops; //setup var_screen_info zionvga_encode_var(&default_var); zion_fb_info.fb_info.var = default_var; zionvga_encode_fix(&zion_fb_info.fb_info.fix); zion_fb_info.fb_info.par = &zion_current_par; // This should give a reasonable default video mode ret = fb_alloc_cmap(&zion_fb_info.fb_info.cmap, 256, 0); if(ret){ PERROR( "failed fb_alloc_cmap()\n" ); ret = -ENOMEM; goto fail_alloc_cmap; } if(register_framebuffer(&zion_fb_info.fb_info) < 0){ PERROR("failed register_framebuffer()\n"); ret = -EINVAL; goto fail_reg_fb; } PINFO("fb%d: %s frame buffer device\n", zion_fb_info.fb_info.node, zion_fb_info.fb_info.fix.id); return 0; fail_reg_fb: fb_dealloc_cmap( &zion_fb_info.fb_info.cmap); fail_alloc_cmap: free_pages(zion_fb_info.ram_address, ZIONVGA_VRAM_ORDER); fail_gfp_fb: return ret; }
int zion_set_params(struct zionvga_reset_arg *reset_arg) { u16 reg = 0; int pal_line = reset_arg->pal_line; int spl_line = reset_arg->spl_line; zion_params_t *params = find_zion(0); if(params == NULL){ return -ENODEV; } reg = mbus_readw(MBUS_ADDR(params,ZIONVGA_VGA_SETTING)); reg &= VGA_RSTR_EN; //Don't touch VGA_RSTR_EN bit (It should be set by TX) if(pal_line==576) { reg |= PAL_LINE_SEL; ZIONVGA_Y_RES = 576; } else if(pal_line==480) { reg &= ~PAL_LINE_SEL; ZIONVGA_Y_RES = 480; } else { PERROR("Unsupported VGA SIZE : PAL-Line=%d",pal_line); return -EINVAL; } if(spl_line==720) { reg |= SPL_SEL; ZIONVGA_X_RES = 720; } else if(spl_line==640) { reg &= ~SPL_SEL; ZIONVGA_X_RES = 640; } else { PERROR("Unsupported VGA SIZE : SPL-Line=%d",spl_line); return -EINVAL; } #if defined(CONFIG_P2PF_K240) || defined(CONFIG_P2PF_K202) || defined(CONFIG_P2PF_K246A) reg |= (CSC_EN); #else reg |= (CSC_EN|TRS_ON); #endif //CONFIG_P2PF_K240 || CONFIG_P2PF_K246A mbus_writew(reg, MBUS_ADDR(params,ZIONVGA_VGA_SETTING)); // Just for assurance reg = mbus_readw(MBUS_ADDR(params,ZIONVGA_VGA_SETTING)); zionvga_encode_var( &default_var ); zion_fb_info.fb_info.var = default_var; return 0; }
/** make proc filesystem **/ int zion_proc_read(char *buf, char **start, off_t offset, int length, int *eof, void *data) { zion_params_t *zion_params; int j; u32 val=0; u16 revision; int len=0; zion_params = find_zion(0); if(zion_params==NULL) { return 0; } revision = mbus_readw(MBUS_ADDR(zion_params,0)); len += sprintf(buf+len, "ZION (Rev. %04X):\n" " Base Address:\n" " MBusAddr=0x%X(%d byte) WorkRAM=0x%X(%d byte)\n" " SDRAM=0x%X(%d byte) Partial-SDRAM=0x%X(%d byte)\n" " Resources:\n" " Bus=%d Dev=%d Func=%d IRQ=%d\n" " Driver:\n" " Version: %s.%s.%s\n", revision, zion_params->mbus_addr, zion_params->mbus_size, zion_params->wram_addr, zion_params->wram_size, zion_params->whole_sdram_addr, zion_params->whole_sdram_size, zion_params->partial_sdram_addr, zion_params->partial_sdram_size, (zion_params->dev->bus)->number, (zion_params->dev->devfn) >> 3, (zion_params->dev->devfn) & 0x07,zion_params->dev->irq, ZIONDRV_MAJOR_VER, ZIONDRV_MINOR_VER, ZIONDRV_PATCH_LEV); len += sprintf(buf + len," (VENDOR_ID=%04X,", zion_params->dev->vendor); len += sprintf(buf + len," DEVICE_ID=%04X)\n", zion_params->dev->device); len+= sprintf(buf+len, " PCI Config Regs. : \n"); for (j = 0; j < 256; j += 4) { if ((j % 32) == 0) { len += sprintf(buf + len,"0x%02X : ", j); } pci_read_config_dword(zion_params->dev, j, &val); len += sprintf(buf + len,"%08X ", val); if ((j % 32) == 28) { len += sprintf(buf + len,"\n"); } } len -= offset; if(len < length) { *eof = 1; if(len <= 0) return 0; } else { len = length; } *start = buf + offset; return len; }