/* dump current cir register contents */
static void cir_dump_regs(struct fintek_dev *fintek)
{
fintek_config_mode_enable(fintek);
fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
pr_info("%s: Dump CIR logical device registers:\n", FINTEK_DRIVER_NAME);
pr_info(" * CR CIR BASE ADDR: 0x%x\n",
(fintek_cr_read(fintek, CIR_CR_BASE_ADDR_HI) << 8) |
fintek_cr_read(fintek, CIR_CR_BASE_ADDR_LO));
pr_info(" * CR CIR IRQ NUM: 0x%x\n",
fintek_cr_read(fintek, CIR_CR_IRQ_SEL));
fintek_config_mode_disable(fintek);
pr_info("%s: Dump CIR registers:\n", FINTEK_DRIVER_NAME);
pr_info(" * STATUS: 0x%x\n",
fintek_cir_reg_read(fintek, CIR_STATUS));
pr_info(" * CONTROL: 0x%x\n",
fintek_cir_reg_read(fintek, CIR_CONTROL));
pr_info(" * RX_DATA: 0x%x\n",
fintek_cir_reg_read(fintek, CIR_RX_DATA));
pr_info(" * TX_CONTROL: 0x%x\n",
fintek_cir_reg_read(fintek, CIR_TX_CONTROL));
pr_info(" * TX_DATA: 0x%x\n",
fintek_cir_reg_read(fintek, CIR_TX_DATA));
}
/* detect hardware features */
static int fintek_hw_detect(struct fintek_dev *fintek)
{
unsigned long flags;
u8 chip_major, chip_minor;
u8 vendor_major, vendor_minor;
u8 portsel, ir_class;
u16 vendor;
int ret = 0;
fintek_config_mode_enable(fintek);
/* Check if we're using config port 0x4e or 0x2e */
portsel = fintek_cr_read(fintek, GCR_CONFIG_PORT_SEL);
if (portsel == 0xff) {
fit_pr(KERN_INFO, "first portsel read was bunk, trying alt");
fintek_config_mode_disable(fintek);
fintek->cr_ip = CR_INDEX_PORT2;
fintek->cr_dp = CR_DATA_PORT2;
fintek_config_mode_enable(fintek);
portsel = fintek_cr_read(fintek, GCR_CONFIG_PORT_SEL);
}
fit_dbg("portsel reg: 0x%02x", portsel);
ir_class = fintek_cir_reg_read(fintek, CIR_CR_CLASS);
fit_dbg("ir_class reg: 0x%02x", ir_class);
switch (ir_class) {
case CLASS_RX_2TX:
case CLASS_RX_1TX:
fintek->hw_tx_capable = true;
break;
case CLASS_RX_ONLY:
default:
fintek->hw_tx_capable = false;
break;
}
chip_major = fintek_cr_read(fintek, GCR_CHIP_ID_HI);
chip_minor = fintek_cr_read(fintek, GCR_CHIP_ID_LO);
vendor_major = fintek_cr_read(fintek, GCR_VENDOR_ID_HI);
vendor_minor = fintek_cr_read(fintek, GCR_VENDOR_ID_LO);
vendor = vendor_major << 8 | vendor_minor;
if (vendor != VENDOR_ID_FINTEK)
fit_pr(KERN_WARNING, "Unknown vendor ID: 0x%04x", vendor);
else
fit_dbg("Read Fintek vendor ID from chip");
fintek_config_mode_disable(fintek);
spin_lock_irqsave(&fintek->fintek_lock, flags);
fintek->chip_major = chip_major;
fintek->chip_minor = chip_minor;
fintek->chip_vendor = vendor;
spin_unlock_irqrestore(&fintek->fintek_lock, flags);
return ret;
}
/* clear config register bit without changing other bits */
static inline void fintek_clear_reg_bit(struct fintek_dev *fintek, u8 val, u8 reg)
{
u8 tmp = fintek_cr_read(fintek, reg) & ~val;
fintek_cr_write(fintek, tmp, reg);
}
