void
nilopt(Prog *firstp)
{
NilFlow *r;
Prog *p;
Graph *g;
int ncheck, nkill;
g = flowstart(firstp, sizeof(NilFlow));
if(g == nil)
return;
if(debug_checknil > 1 /* || strcmp(curfn->nname->sym->name, "f1") == 0 */)
dumpit("nilopt", g->start, 0);
ncheck = 0;
nkill = 0;
for(r = (NilFlow*)g->start; r != nil; r = (NilFlow*)r->f.link) {
p = r->f.prog;
if(p->as != ACHECKNIL || !regtyp(&p->from))
continue;
ncheck++;
if(stackaddr(&p->from)) {
if(debug_checknil && p->lineno > 1)
warnl(p->lineno, "removed nil check of SP address");
r->kill = 1;
continue;
}
nilwalkfwd(r);
if(r->kill) {
if(debug_checknil && p->lineno > 1)
warnl(p->lineno, "removed nil check before indirect");
continue;
}
nilwalkback(r);
if(r->kill) {
if(debug_checknil && p->lineno > 1)
warnl(p->lineno, "removed repeated nil check");
continue;
}
}
for(r = (NilFlow*)g->start; r != nil; r = (NilFlow*)r->f.link) {
if(r->kill) {
nkill++;
excise(&r->f);
}
}
flowend(g);
if(debug_checknil > 1)
print("%S: removed %d of %d nil checks\n", curfn->nname->sym, nkill, ncheck);
}
void
regopt(Prog *firstp)
{
Reg *r, *r1;
Prog *p;
Graph *g;
ProgInfo info;
int i, z;
uint32 vreg;
Bits bit;
if(first) {
fmtinstall('Q', Qconv);
exregoffset = D_R15;
first = 0;
}
mergetemp(firstp);
/*
* control flow is more complicated in generated go code
* than in generated c code. define pseudo-variables for
* registers, so we have complete register usage information.
*/
nvar = NREGVAR;
memset(var, 0, NREGVAR*sizeof var[0]);
for(i=0; i<NREGVAR; i++) {
if(regnodes[i] == N)
regnodes[i] = newname(lookup(regname[i]));
var[i].node = regnodes[i];
}
regbits = RtoB(D_SP);
for(z=0; z<BITS; z++) {
externs.b[z] = 0;
params.b[z] = 0;
consts.b[z] = 0;
addrs.b[z] = 0;
ovar.b[z] = 0;
}
// build list of return variables
setoutvar();
/*
* pass 1
* build aux data structure
* allocate pcs
* find use and set of variables
*/
g = flowstart(firstp, sizeof(Reg));
if(g == nil)
return;
firstr = (Reg*)g->start;
for(r = firstr; r != R; r = (Reg*)r->f.link) {
p = r->f.prog;
if(p->as == AVARDEF)
continue;
proginfo(&info, p);
// Avoid making variables for direct-called functions.
if(p->as == ACALL && p->to.type == D_EXTERN)
continue;
r->use1.b[0] |= info.reguse | info.regindex;
r->set.b[0] |= info.regset;
bit = mkvar(r, &p->from);
if(bany(&bit)) {
if(info.flags & LeftAddr)
setaddrs(bit);
if(info.flags & LeftRead)
for(z=0; z<BITS; z++)
r->use1.b[z] |= bit.b[z];
if(info.flags & LeftWrite)
for(z=0; z<BITS; z++)
r->set.b[z] |= bit.b[z];
}
bit = mkvar(r, &p->to);
if(bany(&bit)) {
if(info.flags & RightAddr)
setaddrs(bit);
if(info.flags & RightRead)
for(z=0; z<BITS; z++)
r->use2.b[z] |= bit.b[z];
if(info.flags & RightWrite)
for(z=0; z<BITS; z++)
r->set.b[z] |= bit.b[z];
}
}
for(i=0; i<nvar; i++) {
Var *v = var+i;
if(v->addr) {
bit = blsh(i);
for(z=0; z<BITS; z++)
addrs.b[z] |= bit.b[z];
}
if(debug['R'] && debug['v'])
print("bit=%2d addr=%d et=%-6E w=%-2d s=%N + %lld\n",
i, v->addr, v->etype, v->width, v->node, v->offset);
}
if(debug['R'] && debug['v'])
dumpit("pass1", &firstr->f, 1);
/*
* pass 2
* find looping structure
*/
flowrpo(g);
if(debug['R'] && debug['v'])
dumpit("pass2", &firstr->f, 1);
/*
* pass 3
* iterate propagating usage
* back until flow graph is complete
*/
loop1:
change = 0;
for(r = firstr; r != R; r = (Reg*)r->f.link)
r->f.active = 0;
for(r = firstr; r != R; r = (Reg*)r->f.link)
if(r->f.prog->as == ARET)
prop(r, zbits, zbits);
loop11:
/* pick up unreachable code */
i = 0;
for(r = firstr; r != R; r = r1) {
r1 = (Reg*)r->f.link;
if(r1 && r1->f.active && !r->f.active) {
prop(r, zbits, zbits);
i = 1;
}
}
if(i)
goto loop11;
if(change)
goto loop1;
if(debug['R'] && debug['v'])
dumpit("pass3", &firstr->f, 1);
/*
* pass 4
* iterate propagating register/variable synchrony
* forward until graph is complete
*/
loop2:
change = 0;
for(r = firstr; r != R; r = (Reg*)r->f.link)
r->f.active = 0;
synch(firstr, zbits);
if(change)
goto loop2;
if(debug['R'] && debug['v'])
dumpit("pass4", &firstr->f, 1);
/*
* pass 4.5
* move register pseudo-variables into regu.
*/
for(r = firstr; r != R; r = (Reg*)r->f.link) {
r->regu = (r->refbehind.b[0] | r->set.b[0]) & REGBITS;
r->set.b[0] &= ~REGBITS;
r->use1.b[0] &= ~REGBITS;
r->use2.b[0] &= ~REGBITS;
r->refbehind.b[0] &= ~REGBITS;
r->refahead.b[0] &= ~REGBITS;
r->calbehind.b[0] &= ~REGBITS;
r->calahead.b[0] &= ~REGBITS;
r->regdiff.b[0] &= ~REGBITS;
r->act.b[0] &= ~REGBITS;
}
/*
* pass 5
* isolate regions
* calculate costs (paint1)
*/
r = firstr;
if(r) {
for(z=0; z<BITS; z++)
bit.b[z] = (r->refahead.b[z] | r->calahead.b[z]) &
~(externs.b[z] | params.b[z] | addrs.b[z] | consts.b[z]);
if(bany(&bit) && !r->f.refset) {
// should never happen - all variables are preset
if(debug['w'])
print("%L: used and not set: %Q\n", r->f.prog->lineno, bit);
r->f.refset = 1;
}
}
for(r = firstr; r != R; r = (Reg*)r->f.link)
r->act = zbits;
rgp = region;
nregion = 0;
for(r = firstr; r != R; r = (Reg*)r->f.link) {
for(z=0; z<BITS; z++)
bit.b[z] = r->set.b[z] &
~(r->refahead.b[z] | r->calahead.b[z] | addrs.b[z]);
if(bany(&bit) && !r->f.refset) {
if(debug['w'])
print("%L: set and not used: %Q\n", r->f.prog->lineno, bit);
r->f.refset = 1;
excise(&r->f);
}
for(z=0; z<BITS; z++)
bit.b[z] = LOAD(r) & ~(r->act.b[z] | addrs.b[z]);
while(bany(&bit)) {
i = bnum(bit);
rgp->enter = r;
rgp->varno = i;
change = 0;
paint1(r, i);
bit.b[i/32] &= ~(1L<<(i%32));
if(change <= 0)
continue;
rgp->cost = change;
nregion++;
if(nregion >= NRGN) {
if(debug['R'] && debug['v'])
print("too many regions\n");
goto brk;
}
rgp++;
}
}
brk:
qsort(region, nregion, sizeof(region[0]), rcmp);
if(debug['R'] && debug['v'])
dumpit("pass5", &firstr->f, 1);
/*
* pass 6
* determine used registers (paint2)
* replace code (paint3)
*/
rgp = region;
for(i=0; i<nregion; i++) {
bit = blsh(rgp->varno);
vreg = paint2(rgp->enter, rgp->varno);
vreg = allreg(vreg, rgp);
if(rgp->regno != 0) {
if(debug['R'] && debug['v']) {
Var *v;
v = var + rgp->varno;
print("registerize %N+%lld (bit=%2d et=%2E) in %R\n",
v->node, v->offset, rgp->varno, v->etype, rgp->regno);
}
paint3(rgp->enter, rgp->varno, vreg, rgp->regno);
}
rgp++;
}
if(debug['R'] && debug['v'])
dumpit("pass6", &firstr->f, 1);
/*
* free aux structures. peep allocates new ones.
*/
flowend(g);
firstr = R;
/*
* pass 7
* peep-hole on basic block
*/
if(!debug['R'] || debug['P'])
peep(firstp);
/*
* eliminate nops
*/
for(p=firstp; p!=P; p=p->link) {
while(p->link != P && p->link->as == ANOP)
p->link = p->link->link;
if(p->to.type == D_BRANCH)
while(p->to.u.branch != P && p->to.u.branch->as == ANOP)
p->to.u.branch = p->to.u.branch->link;
}
if(debug['R']) {
if(ostats.ncvtreg ||
ostats.nspill ||
ostats.nreload ||
ostats.ndelmov ||
ostats.nvar ||
ostats.naddr ||
0)
print("\nstats\n");
if(ostats.ncvtreg)
print(" %4d cvtreg\n", ostats.ncvtreg);
if(ostats.nspill)
print(" %4d spill\n", ostats.nspill);
if(ostats.nreload)
print(" %4d reload\n", ostats.nreload);
if(ostats.ndelmov)
print(" %4d delmov\n", ostats.ndelmov);
if(ostats.nvar)
print(" %4d var\n", ostats.nvar);
if(ostats.naddr)
print(" %4d addr\n", ostats.naddr);
memset(&ostats, 0, sizeof(ostats));
}
}
void
peep(Prog *firstp)
{
Flow *r, *r1;
Graph *g;
Prog *p, *p1;
int t;
g = flowstart(firstp, sizeof(Flow));
if(g == nil)
return;
for(r=g->start, t=0; r!=nil; r=r->link, t++)
r->active = t;
// byte, word arithmetic elimination.
elimshortmov(g);
// constant propagation
// find MOV $con,R followed by
// another MOV $con,R without
// setting R in the interim
for(r=g->start; r!=nil; r=r->link) {
p = r->prog;
switch(p->as) {
case ALEAL:
case ALEAQ:
if(regtyp(&p->to))
if(p->from.sym != S)
if(p->from.index == D_NONE || p->from.index == D_CONST)
conprop(r);
break;
case AMOVB:
case AMOVW:
case AMOVL:
case AMOVQ:
case AMOVSS:
case AMOVSD:
if(regtyp(&p->to))
if(p->from.type == D_CONST)
conprop(r);
break;
}
}
loop1:
if(debug['P'] && debug['v'])
dumpit("loop1", g->start, 0);
t = 0;
for(r=g->start; r!=nil; r=r->link) {
p = r->prog;
switch(p->as) {
case AMOVL:
case AMOVQ:
case AMOVSS:
case AMOVSD:
if(regtyp(&p->to))
if(regtyp(&p->from)) {
if(copyprop(g, r)) {
excise(r);
t++;
} else
if(subprop(r) && copyprop(g, r)) {
excise(r);
t++;
}
}
break;
case AMOVBLZX:
case AMOVWLZX:
case AMOVBLSX:
case AMOVWLSX:
if(regtyp(&p->to)) {
r1 = rnops(uniqs(r));
if(r1 != nil) {
p1 = r1->prog;
if(p->as == p1->as && p->to.type == p1->from.type){
p1->as = AMOVL;
t++;
}
}
}
break;
case AMOVBQSX:
case AMOVBQZX:
case AMOVWQSX:
case AMOVWQZX:
case AMOVLQSX:
case AMOVLQZX:
case AMOVQL:
if(regtyp(&p->to)) {
r1 = rnops(uniqs(r));
if(r1 != nil) {
p1 = r1->prog;
if(p->as == p1->as && p->to.type == p1->from.type){
p1->as = AMOVQ;
t++;
}
}
}
break;
case AADDL:
case AADDQ:
case AADDW:
if(p->from.type != D_CONST || needc(p->link))
break;
if(p->from.offset == -1){
if(p->as == AADDQ)
p->as = ADECQ;
else
if(p->as == AADDL)
p->as = ADECL;
else
p->as = ADECW;
p->from = zprog.from;
break;
}
if(p->from.offset == 1){
if(p->as == AADDQ)
p->as = AINCQ;
else if(p->as == AADDL)
p->as = AINCL;
else
p->as = AINCW;
p->from = zprog.from;
break;
}
break;
case ASUBL:
case ASUBQ:
case ASUBW:
if(p->from.type != D_CONST || needc(p->link))
break;
if(p->from.offset == -1) {
if(p->as == ASUBQ)
p->as = AINCQ;
else
if(p->as == ASUBL)
p->as = AINCL;
else
p->as = AINCW;
p->from = zprog.from;
break;
}
if(p->from.offset == 1){
if(p->as == ASUBQ)
p->as = ADECQ;
else
if(p->as == ASUBL)
p->as = ADECL;
else
p->as = ADECW;
p->from = zprog.from;
break;
}
break;
}
}
if(t)
goto loop1;
// MOVLQZX removal.
// The MOVLQZX exists to avoid being confused for a
// MOVL that is just copying 32-bit data around during
// copyprop. Now that copyprop is done, remov MOVLQZX R1, R2
// if it is dominated by an earlier ADDL/MOVL/etc into R1 that
// will have already cleared the high bits.
//
// MOVSD removal.
// We never use packed registers, so a MOVSD between registers
// can be replaced by MOVAPD, which moves the pair of float64s
// instead of just the lower one. We only use the lower one, but
// the processor can do better if we do moves using both.
for(r=g->start; r!=nil; r=r->link) {
p = r->prog;
if(p->as == AMOVLQZX)
if(regtyp(&p->from))
if(p->from.type == p->to.type)
if(prevl(r, p->from.type))
excise(r);
if(p->as == AMOVSD)
if(regtyp(&p->from))
if(regtyp(&p->to))
p->as = AMOVAPD;
}
// load pipelining
// push any load from memory as early as possible
// to give it time to complete before use.
for(r=g->start; r!=nil; r=r->link) {
p = r->prog;
switch(p->as) {
case AMOVB:
case AMOVW:
case AMOVL:
case AMOVQ:
case AMOVLQZX:
if(regtyp(&p->to) && !regconsttyp(&p->from))
pushback(r);
}
}
flowend(g);
}
void
regopt(Prog *firstp)
{
Reg *r, *r1;
Prog *p;
Graph *g;
int i, z;
uint32 vreg;
Bits bit;
ProgInfo info;
if(first) {
fmtinstall('Q', Qconv);
first = 0;
}
fixjmp(firstp);
mergetemp(firstp);
/*
* control flow is more complicated in generated go code
* than in generated c code. define pseudo-variables for
* registers, so we have complete register usage information.
*/
nvar = NREGVAR;
memset(var, 0, NREGVAR*sizeof var[0]);
for(i=0; i<NREGVAR; i++) {
if(regnodes[i] == N)
regnodes[i] = newname(lookup(regname[i]));
var[i].node = regnodes[i];
}
regbits = RtoB(REGSP)|RtoB(REGLINK)|RtoB(REGPC);
for(z=0; z<BITS; z++) {
externs.b[z] = 0;
params.b[z] = 0;
consts.b[z] = 0;
addrs.b[z] = 0;
ovar.b[z] = 0;
}
// build list of return variables
setoutvar();
/*
* pass 1
* build aux data structure
* allocate pcs
* find use and set of variables
*/
g = flowstart(firstp, sizeof(Reg));
if(g == nil)
return;
firstr = (Reg*)g->start;
for(r = firstr; r != R; r = (Reg*)r->f.link) {
p = r->f.prog;
proginfo(&info, p);
// Avoid making variables for direct-called functions.
if(p->as == ABL && p->to.type == D_EXTERN)
continue;
bit = mkvar(r, &p->from);
if(info.flags & LeftRead)
for(z=0; z<BITS; z++)
r->use1.b[z] |= bit.b[z];
if(info.flags & LeftAddr)
setaddrs(bit);
if(info.flags & RegRead) {
if(p->from.type != D_FREG)
r->use1.b[0] |= RtoB(p->reg);
else
r->use1.b[0] |= FtoB(p->reg);
}
if(info.flags & (RightAddr | RightRead | RightWrite)) {
bit = mkvar(r, &p->to);
if(info.flags & RightAddr)
setaddrs(bit);
if(info.flags & RightRead)
for(z=0; z<BITS; z++)
r->use2.b[z] |= bit.b[z];
if(info.flags & RightWrite)
for(z=0; z<BITS; z++)
r->set.b[z] |= bit.b[z];
}
}
if(firstr == R)
return;
for(i=0; i<nvar; i++) {
Var *v = var+i;
if(v->addr) {
bit = blsh(i);
for(z=0; z<BITS; z++)
addrs.b[z] |= bit.b[z];
}
if(debug['R'] && debug['v'])
print("bit=%2d addr=%d et=%-6E w=%-2d s=%N + %lld\n",
i, v->addr, v->etype, v->width, v->node, v->offset);
}
if(debug['R'] && debug['v'])
dumpit("pass1", &firstr->f, 1);
/*
* pass 2
* find looping structure
*/
flowrpo(g);
if(debug['R'] && debug['v'])
dumpit("pass2", &firstr->f, 1);
/*
* pass 3
* iterate propagating usage
* back until flow graph is complete
*/
loop1:
change = 0;
for(r = firstr; r != R; r = (Reg*)r->f.link)
r->f.active = 0;
for(r = firstr; r != R; r = (Reg*)r->f.link)
if(r->f.prog->as == ARET)
prop(r, zbits, zbits);
loop11:
/* pick up unreachable code */
i = 0;
for(r = firstr; r != R; r = r1) {
r1 = (Reg*)r->f.link;
if(r1 && r1->f.active && !r->f.active) {
prop(r, zbits, zbits);
i = 1;
}
}
if(i)
goto loop11;
if(change)
goto loop1;
if(debug['R'] && debug['v'])
dumpit("pass3", &firstr->f, 1);
/*
* pass 4
* iterate propagating register/variable synchrony
* forward until graph is complete
*/
loop2:
change = 0;
for(r = firstr; r != R; r = (Reg*)r->f.link)
r->f.active = 0;
synch(firstr, zbits);
if(change)
goto loop2;
addsplits();
if(debug['R'] && debug['v'])
dumpit("pass4", &firstr->f, 1);
if(debug['R'] > 1) {
print("\nprop structure:\n");
for(r = firstr; r != R; r = (Reg*)r->f.link) {
print("%d:%P", r->f.loop, r->f.prog);
for(z=0; z<BITS; z++) {
bit.b[z] = r->set.b[z] |
r->refahead.b[z] | r->calahead.b[z] |
r->refbehind.b[z] | r->calbehind.b[z] |
r->use1.b[z] | r->use2.b[z];
bit.b[z] &= ~addrs.b[z];
}
if(bany(&bit)) {
print("\t");
if(bany(&r->use1))
print(" u1=%Q", r->use1);
if(bany(&r->use2))
print(" u2=%Q", r->use2);
if(bany(&r->set))
print(" st=%Q", r->set);
if(bany(&r->refahead))
print(" ra=%Q", r->refahead);
if(bany(&r->calahead))
print(" ca=%Q", r->calahead);
if(bany(&r->refbehind))
print(" rb=%Q", r->refbehind);
if(bany(&r->calbehind))
print(" cb=%Q", r->calbehind);
}
print("\n");
}
}
/*
* pass 4.5
* move register pseudo-variables into regu.
*/
for(r = firstr; r != R; r = (Reg*)r->f.link) {
r->regu = (r->refbehind.b[0] | r->set.b[0]) & REGBITS;
r->set.b[0] &= ~REGBITS;
r->use1.b[0] &= ~REGBITS;
r->use2.b[0] &= ~REGBITS;
r->refbehind.b[0] &= ~REGBITS;
r->refahead.b[0] &= ~REGBITS;
r->calbehind.b[0] &= ~REGBITS;
r->calahead.b[0] &= ~REGBITS;
r->regdiff.b[0] &= ~REGBITS;
r->act.b[0] &= ~REGBITS;
}
if(debug['R'] && debug['v'])
dumpit("pass4.5", &firstr->f, 1);
/*
* pass 5
* isolate regions
* calculate costs (paint1)
*/
r = firstr;
if(r) {
for(z=0; z<BITS; z++)
bit.b[z] = (r->refahead.b[z] | r->calahead.b[z]) &
~(externs.b[z] | params.b[z] | addrs.b[z] | consts.b[z]);
if(bany(&bit) & !r->f.refset) {
// should never happen - all variables are preset
if(debug['w'])
print("%L: used and not set: %Q\n", r->f.prog->lineno, bit);
r->f.refset = 1;
}
}
for(r = firstr; r != R; r = (Reg*)r->f.link)
r->act = zbits;
rgp = region;
nregion = 0;
for(r = firstr; r != R; r = (Reg*)r->f.link) {
for(z=0; z<BITS; z++)
bit.b[z] = r->set.b[z] &
~(r->refahead.b[z] | r->calahead.b[z] | addrs.b[z]);
if(bany(&bit) && !r->f.refset) {
if(debug['w'])
print("%L: set and not used: %Q\n", r->f.prog->lineno, bit);
r->f.refset = 1;
excise(&r->f);
}
for(z=0; z<BITS; z++)
bit.b[z] = LOAD(r) & ~(r->act.b[z] | addrs.b[z]);
while(bany(&bit)) {
i = bnum(bit);
rgp->enter = r;
rgp->varno = i;
change = 0;
if(debug['R'] > 1)
print("\n");
paint1(r, i);
bit.b[i/32] &= ~(1L<<(i%32));
if(change <= 0) {
if(debug['R'])
print("%L $%d: %Q\n",
r->f.prog->lineno, change, blsh(i));
continue;
}
rgp->cost = change;
nregion++;
if(nregion >= NRGN) {
if(debug['R'] > 1)
print("too many regions\n");
goto brk;
}
rgp++;
}
}
brk:
qsort(region, nregion, sizeof(region[0]), rcmp);
if(debug['R'] && debug['v'])
dumpit("pass5", &firstr->f, 1);
/*
* pass 6
* determine used registers (paint2)
* replace code (paint3)
*/
rgp = region;
for(i=0; i<nregion; i++) {
bit = blsh(rgp->varno);
vreg = paint2(rgp->enter, rgp->varno);
vreg = allreg(vreg, rgp);
if(debug['R']) {
if(rgp->regno >= NREG)
print("%L $%d F%d: %Q\n",
rgp->enter->f.prog->lineno,
rgp->cost,
rgp->regno-NREG,
bit);
else
print("%L $%d R%d: %Q\n",
rgp->enter->f.prog->lineno,
rgp->cost,
rgp->regno,
bit);
}
if(rgp->regno != 0)
paint3(rgp->enter, rgp->varno, vreg, rgp->regno);
rgp++;
}
if(debug['R'] && debug['v'])
dumpit("pass6", &firstr->f, 1);
/*
* pass 7
* peep-hole on basic block
*/
if(!debug['R'] || debug['P']) {
peep(firstp);
}
if(debug['R'] && debug['v'])
dumpit("pass7", &firstr->f, 1);
/*
* last pass
* eliminate nops
* free aux structures
* adjust the stack pointer
* MOVW.W R1,-12(R13) <<- start
* MOVW R0,R1
* MOVW R1,8(R13)
* MOVW $0,R1
* MOVW R1,4(R13)
* BL ,runtime.newproc+0(SB)
* MOVW &ft+-32(SP),R7 <<- adjust
* MOVW &j+-40(SP),R6 <<- adjust
* MOVW autotmp_0003+-24(SP),R5 <<- adjust
* MOVW $12(R13),R13 <<- finish
*/
vreg = 0;
for(p = firstp; p != P; p = p->link) {
while(p->link != P && p->link->as == ANOP)
p->link = p->link->link;
if(p->to.type == D_BRANCH)
while(p->to.u.branch != P && p->to.u.branch->as == ANOP)
p->to.u.branch = p->to.u.branch->link;
if(p->as == AMOVW && p->to.reg == 13) {
if(p->scond & C_WBIT) {
vreg = -p->to.offset; // in adjust region
// print("%P adjusting %d\n", p, vreg);
continue;
}
if(p->from.type == D_CONST && p->to.type == D_REG) {
if(p->from.offset != vreg)
print("in and out different\n");
// print("%P finish %d\n", p, vreg);
vreg = 0; // done adjust region
continue;
}
// print("%P %d %d from type\n", p, p->from.type, D_CONST);
// print("%P %d %d to type\n\n", p, p->to.type, D_REG);
}
if(p->as == AMOVW && vreg != 0) {
if(p->from.sym != S)
if(p->from.name == D_AUTO || p->from.name == D_PARAM) {
p->from.offset += vreg;
// print("%P adjusting from %d %d\n", p, vreg, p->from.type);
}
if(p->to.sym != S)
if(p->to.name == D_AUTO || p->to.name == D_PARAM) {
p->to.offset += vreg;
// print("%P adjusting to %d %d\n", p, vreg, p->from.type);
}
}
}
flowend(g);
}
void
peep(Prog *firstp)
{
Flow *r, *r1;
Graph *g;
Prog *p, *p1;
int t;
g = flowstart(firstp, sizeof(Flow));
if(g == nil)
return;
for(r=g->start, t=0; r!=nil; r=r->link, t++)
r->active = t;
// byte, word arithmetic elimination.
elimshortmov(g);
// constant propagation
// find MOV $con,R followed by
// another MOV $con,R without
// setting R in the interim
for(r=g->start; r!=nil; r=r->link) {
p = r->prog;
switch(p->as) {
case ALEAL:
if(regtyp(&p->to))
if(p->from.sym != S)
if(p->from.index == D_NONE || p->from.index == D_CONST)
conprop(r);
break;
case AMOVB:
case AMOVW:
case AMOVL:
case AMOVSS:
case AMOVSD:
if(regtyp(&p->to))
if(p->from.type == D_CONST)
conprop(r);
break;
}
}
loop1:
if(debug['P'] && debug['v'])
dumpit("loop1", g->start, 0);
t = 0;
for(r=g->start; r!=nil; r=r->link) {
p = r->prog;
switch(p->as) {
case AMOVL:
case AMOVSS:
case AMOVSD:
if(regtyp(&p->to))
if(regtyp(&p->from)) {
if(copyprop(g, r)) {
excise(r);
t++;
} else
if(subprop(r) && copyprop(g, r)) {
excise(r);
t++;
}
}
break;
case AMOVBLZX:
case AMOVWLZX:
case AMOVBLSX:
case AMOVWLSX:
if(regtyp(&p->to)) {
r1 = rnops(uniqs(r));
if(r1 != nil) {
p1 = r1->prog;
if(p->as == p1->as && p->to.type == p1->from.type){
p1->as = AMOVL;
t++;
}
}
}
break;
case AADDL:
case AADDW:
if(p->from.type != D_CONST || needc(p->link))
break;
if(p->from.offset == -1){
if(p->as == AADDL)
p->as = ADECL;
else
p->as = ADECW;
p->from = zprog.from;
break;
}
if(p->from.offset == 1){
if(p->as == AADDL)
p->as = AINCL;
else
p->as = AINCW;
p->from = zprog.from;
break;
}
break;
case ASUBL:
case ASUBW:
if(p->from.type != D_CONST || needc(p->link))
break;
if(p->from.offset == -1) {
if(p->as == ASUBL)
p->as = AINCL;
else
p->as = AINCW;
p->from = zprog.from;
break;
}
if(p->from.offset == 1){
if(p->as == ASUBL)
p->as = ADECL;
else
p->as = ADECW;
p->from = zprog.from;
break;
}
break;
}
}
if(t)
goto loop1;
// MOVSD removal.
// We never use packed registers, so a MOVSD between registers
// can be replaced by MOVAPD, which moves the pair of float64s
// instead of just the lower one. We only use the lower one, but
// the processor can do better if we do moves using both.
for(r=g->start; r!=nil; r=r->link) {
p = r->prog;
if(p->as == AMOVSD)
if(regtyp(&p->from))
if(regtyp(&p->to))
p->as = AMOVAPD;
}
flowend(g);
}
void
mergetemp(Prog *firstp)
{
int i, j, nvar, ninuse, nfree, nkill;
TempVar *var, *v, *v1, **bystart, **inuse;
TempFlow *r;
NodeList *l, **lp;
Node *n;
Prog *p, *p1;
Type *t;
ProgInfo info, info1;
int32 gen;
Graph *g;
enum { Debug = 0 };
g = flowstart(firstp, sizeof(TempFlow));
if(g == nil)
return;
// Build list of all mergeable variables.
nvar = 0;
for(l = curfn->dcl; l != nil; l = l->next)
if(canmerge(l->n))
nvar++;
var = calloc(nvar*sizeof var[0], 1);
nvar = 0;
for(l = curfn->dcl; l != nil; l = l->next) {
n = l->n;
if(canmerge(n)) {
v = &var[nvar++];
n->opt = v;
v->node = n;
}
}
// Build list of uses.
// We assume that the earliest reference to a temporary is its definition.
// This is not true of variables in general but our temporaries are all
// single-use (that's why we have so many!).
for(r = (TempFlow*)g->start; r != nil; r = (TempFlow*)r->f.link) {
p = r->f.prog;
proginfo(&info, p);
if(p->from.node != N && p->from.node->opt && p->to.node != N && p->to.node->opt)
fatal("double node %P", p);
if((n = p->from.node) != N && (v = n->opt) != nil ||
(n = p->to.node) != N && (v = n->opt) != nil) {
if(v->def == nil)
v->def = r;
r->uselink = v->use;
v->use = r;
if(n == p->from.node && (info.flags & LeftAddr))
v->addr = 1;
}
}
if(Debug > 1)
dumpit("before", g->start, 0);
nkill = 0;
// Special case.
for(v = var; v < var+nvar; v++) {
if(v->addr)
continue;
// Used in only one instruction, which had better be a write.
if((r = v->use) != nil && r->uselink == nil) {
p = r->f.prog;
proginfo(&info, p);
if(p->to.node == v->node && (info.flags & RightWrite) && !(info.flags & RightRead)) {
p->as = ANOP;
p->to = zprog.to;
v->removed = 1;
if(Debug)
print("drop write-only %S\n", v->node->sym);
} else
fatal("temp used and not set: %P", p);
nkill++;
continue;
}
// Written in one instruction, read in the next, otherwise unused,
// no jumps to the next instruction. Happens mainly in 386 compiler.
if((r = v->use) != nil && r->f.link == &r->uselink->f && r->uselink->uselink == nil && uniqp(r->f.link) == &r->f) {
p = r->f.prog;
proginfo(&info, p);
p1 = r->f.link->prog;
proginfo(&info1, p1);
enum {
SizeAny = SizeB | SizeW | SizeL | SizeQ | SizeF | SizeD,
};
if(p->from.node == v->node && p1->to.node == v->node && (info.flags & Move) &&
!((info.flags|info1.flags) & (LeftAddr|RightAddr)) &&
(info.flags & SizeAny) == (info1.flags & SizeAny)) {
p1->from = p->from;
excise(&r->f);
v->removed = 1;
if(Debug)
print("drop immediate-use %S\n", v->node->sym);
}
nkill++;
continue;
}
}
// Traverse live range of each variable to set start, end.
// Each flood uses a new value of gen so that we don't have
// to clear all the r->f.active words after each variable.
gen = 0;
for(v = var; v < var+nvar; v++) {
gen++;
for(r = v->use; r != nil; r = r->uselink)
mergewalk(v, r, gen);
}
// Sort variables by start.
bystart = malloc(nvar*sizeof bystart[0]);
for(i=0; i<nvar; i++)
bystart[i] = &var[i];
qsort(bystart, nvar, sizeof bystart[0], startcmp);
// List of in-use variables, sorted by end, so that the ones that
// will last the longest are the earliest ones in the array.
// The tail inuse[nfree:] holds no-longer-used variables.
// In theory we should use a sorted tree so that insertions are
// guaranteed O(log n) and then the loop is guaranteed O(n log n).
// In practice, it doesn't really matter.
inuse = malloc(nvar*sizeof inuse[0]);
ninuse = 0;
nfree = nvar;
for(i=0; i<nvar; i++) {
v = bystart[i];
if(v->addr || v->removed)
continue;
// Expire no longer in use.
while(ninuse > 0 && inuse[ninuse-1]->end < v->start) {
v1 = inuse[--ninuse];
inuse[--nfree] = v1;
}
// Find old temp to reuse if possible.
t = v->node->type;
for(j=nfree; j<nvar; j++) {
v1 = inuse[j];
if(eqtype(t, v1->node->type)) {
inuse[j] = inuse[nfree++];
if(v1->merge)
v->merge = v1->merge;
else
v->merge = v1;
nkill++;
break;
}
}
// Sort v into inuse.
j = ninuse++;
while(j > 0 && inuse[j-1]->end < v->end) {
inuse[j] = inuse[j-1];
j--;
}
inuse[j] = v;
}
if(Debug) {
print("%S [%d - %d]\n", curfn->nname->sym, nvar, nkill);
for(v=var; v<var+nvar; v++) {
print("var %#N %T %lld-%lld", v->node, v->node->type, v->start, v->end);
if(v->addr)
print(" addr=1");
if(v->removed)
print(" dead=1");
if(v->merge)
print(" merge %#N", v->merge->node);
if(v->start == v->end)
print(" %P", v->def->f.prog);
print("\n");
}
if(Debug > 1)
dumpit("after", g->start, 0);
}
// Update node references to use merged temporaries.
for(r = (TempFlow*)g->start; r != nil; r = (TempFlow*)r->f.link) {
p = r->f.prog;
if((n = p->from.node) != N && (v = n->opt) != nil && v->merge != nil)
p->from.node = v->merge->node;
if((n = p->to.node) != N && (v = n->opt) != nil && v->merge != nil)
p->to.node = v->merge->node;
}
// Delete merged nodes from declaration list.
for(lp = &curfn->dcl; (l = *lp); ) {
curfn->dcl->end = l;
n = l->n;
v = n->opt;
if(v && (v->merge || v->removed)) {
*lp = l->next;
continue;
}
lp = &l->next;
}
// Clear aux structures.
for(v=var; v<var+nvar; v++)
v->node->opt = nil;
free(var);
free(bystart);
free(inuse);
flowend(g);
}
void
peep(Prog *firstp)
{
Flow *r;
Graph *g;
Prog *p;
int t;
g = flowstart(firstp, sizeof(Flow));
if(g == nil)
return;
for(r=g->start, t=0; r!=nil; r=r->link, t++)
r->active = t;
loop1:
if(debug['P'] && debug['v'])
dumpit("loop1", g->start, 0);
t = 0;
for(r=g->start; r!=nil; r=r->link) {
p = r->prog;
switch(p->as) {
case ASLL:
case ASRL:
case ASRA:
/*
* elide shift into D_SHIFT operand of subsequent instruction
*/
// if(shiftprop(r)) {
// excise(r);
// t++;
// break;
// }
break;
case AMOVB:
case AMOVH:
case AMOVW:
case AMOVF:
case AMOVD:
if(regtyp(&p->from))
if(p->from.type == p->to.type)
if(p->scond == C_SCOND_NONE) {
if(copyprop(g, r)) {
excise(r);
t++;
break;
}
if(subprop(r) && copyprop(g, r)) {
excise(r);
t++;
break;
}
}
break;
case AMOVHS:
case AMOVHU:
case AMOVBS:
case AMOVBU:
if(p->from.type == D_REG) {
if(shortprop(r))
t++;
}
break;
#ifdef NOTDEF
if(p->scond == C_SCOND_NONE)
if(regtyp(&p->to))
if(isdconst(&p->from)) {
constprop(&p->from, &p->to, r->s1);
}
break;
#endif
}
}
if(t)
goto loop1;
for(r=g->start; r!=nil; r=r->link) {
p = r->prog;
switch(p->as) {
case AEOR:
/*
* EOR -1,x,y => MVN x,y
*/
if(isdconst(&p->from) && p->from.offset == -1) {
p->as = AMVN;
p->from.type = D_REG;
if(p->reg != NREG)
p->from.reg = p->reg;
else
p->from.reg = p->to.reg;
p->reg = NREG;
}
break;
}
}
for(r=g->start; r!=nil; r=r->link) {
p = r->prog;
switch(p->as) {
case AMOVW:
case AMOVB:
case AMOVBS:
case AMOVBU:
if(p->from.type == D_OREG && p->from.offset == 0)
xtramodes(g, r, &p->from);
else
if(p->to.type == D_OREG && p->to.offset == 0)
xtramodes(g, r, &p->to);
else
continue;
break;
// case ACMP:
// /*
// * elide CMP $0,x if calculation of x can set condition codes
// */
// if(isdconst(&p->from) || p->from.offset != 0)
// continue;
// r2 = r->s1;
// if(r2 == nil)
// continue;
// t = r2->prog->as;
// switch(t) {
// default:
// continue;
// case ABEQ:
// case ABNE:
// case ABMI:
// case ABPL:
// break;
// case ABGE:
// t = ABPL;
// break;
// case ABLT:
// t = ABMI;
// break;
// case ABHI:
// t = ABNE;
// break;
// case ABLS:
// t = ABEQ;
// break;
// }
// r1 = r;
// do
// r1 = uniqp(r1);
// while (r1 != nil && r1->prog->as == ANOP);
// if(r1 == nil)
// continue;
// p1 = r1->prog;
// if(p1->to.type != D_REG)
// continue;
// if(p1->to.reg != p->reg)
// if(!(p1->as == AMOVW && p1->from.type == D_REG && p1->from.reg == p->reg))
// continue;
//
// switch(p1->as) {
// default:
// continue;
// case AMOVW:
// if(p1->from.type != D_REG)
// continue;
// case AAND:
// case AEOR:
// case AORR:
// case ABIC:
// case AMVN:
// case ASUB:
// case ARSB:
// case AADD:
// case AADC:
// case ASBC:
// case ARSC:
// break;
// }
// p1->scond |= C_SBIT;
// r2->prog->as = t;
// excise(r);
// continue;
}
}
// predicate(g);
flowend(g);
}
