/* ************************************************************************ * * Setup the architecture * */ static void __init mpc83xx_km_setup_arch(void) { #ifdef CONFIG_QUICC_ENGINE struct device_node *np; #endif if (ppc_md.progress) ppc_md.progress("kmpbec83xx_setup_arch()", 0); mpc83xx_setup_pci(); #ifdef CONFIG_QUICC_ENGINE np = of_find_node_by_name(NULL, "par_io"); if (np != NULL) { par_io_init(np); of_node_put(np); for_each_node_by_name(np, "spi") par_io_of_config(np); for_each_node_by_name(np, "ucc") par_io_of_config(np); /* Only apply this quirk when par_io is available */ np = of_find_compatible_node(NULL, "network", "ucc_geth"); if (np != NULL) { quirk_mpc8360e_qe_enet10(); of_node_put(np); } } #endif /* CONFIG_QUICC_ENGINE */ }
static void __init mpc85xx_mds_qe_init(void) { struct device_node *np; np = of_find_compatible_node(NULL, NULL, "fsl,qe"); if (!np) { np = of_find_node_by_name(NULL, "qe"); if (!np) return; } if (!of_device_is_available(np)) { of_node_put(np); return; } qe_reset(); of_node_put(np); np = of_find_node_by_name(NULL, "par_io"); if (np) { struct device_node *ucc; par_io_init(np); of_node_put(np); for_each_node_by_name(ucc, "ucc") par_io_of_config(ucc); } mpc85xx_mds_reset_ucc_phys(); if (machine_is(p1021_mds)) { struct ccsr_guts __iomem *guts; np = of_find_node_by_name(NULL, "global-utilities"); if (np) { guts = of_iomap(np, 0); if (!guts) pr_err("mpc85xx-rdb: could not map global utilities register\n"); else{ /* P1021 has pins muxed for QE and other functions. To * enable QE UEC mode, we need to set bit QE0 for UCC1 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9 * and QE12 for QE MII management signals in PMUXCR * register. */ setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | MPC85xx_PMUXCR_QE(3) | MPC85xx_PMUXCR_QE(9) | MPC85xx_PMUXCR_QE(12)); iounmap(guts); } of_node_put(np); } } }
static int __init machine_setup(void) { struct device_node *clock; struct device_node *eth = NULL; for_each_node_by_name(clock, "main-oscillator") update_clock_frequency(clock); if ((eth = of_find_compatible_node(eth, NULL, "opencores,ethoc"))) update_local_mac(eth); return 0; }
void __init mpc85xx_qe_par_io_init(void) { struct device_node *np; np = of_find_node_by_name(NULL, "par_io"); if (np) { struct device_node *ucc; par_io_init(np); of_node_put(np); for_each_node_by_name(ucc, "ucc") par_io_of_config(ucc); } }
/* ************************************************************************ * * Setup the architecture * */ static void __init twr_p1025_setup_arch(void) { #ifdef CONFIG_QUICC_ENGINE struct device_node *np; #endif if (ppc_md.progress) ppc_md.progress("twr_p1025_setup_arch()", 0); mpc85xx_smp_init(); fsl_pci_assign_primary(); #ifdef CONFIG_QUICC_ENGINE np = of_find_compatible_node(NULL, NULL, "fsl,qe"); if (!np) { np = of_find_node_by_name(NULL, "qe"); if (!np) { printk(KERN_ERR "Could not find Quicc Engine node\n"); goto qe_fail; } } qe_reset(); of_node_put(np); np = of_find_node_by_name(NULL, "par_io"); if (np) { struct device_node *ucc; par_io_init(np); of_node_put(np); for_each_node_by_name(ucc, "ucc") par_io_of_config(ucc); } #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) if (machine_is(twr_p1025)) { struct ccsr_guts __iomem *guts; np = of_find_node_by_name(NULL, "global-utilities"); if (np) { guts = of_iomap(np, 0); if (!guts) pr_err("twr_p1025: could not map global utilities register\n"); else { /* P1025 has pins muxed for QE and other functions. To * enable QE UEC mode, we need to set bit QE0 for UCC1 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9 * and QE12 for QE MII management signals in PMUXCR * register. */ printk(KERN_INFO "P1025 pinmux configured for QE\n"); /* Set QE mux bits in PMUXCR */ setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | MPC85xx_PMUXCR_QE(3) | MPC85xx_PMUXCR_QE(9) | MPC85xx_PMUXCR_QE(12)); iounmap(guts); #if defined(CONFIG_SERIAL_QE) || defined(CONFIG_SERIAL_QE_MODULE) /* On P1025TWR board, the UCC7 acted as UART port. * However, The UCC7's CTS pin is low level in default, * it will impact the transmission in full duplex * communication. So disable the Flow control pin PA18. * The UCC7 UART just can use RXD and TXD pins. */ par_io_config_pin(0, 18, 0, 0, 0, 0); #endif /* Drive PB29 to CPLD low - CPLD will then change * muxing from LBC to QE */ par_io_config_pin(1, 29, 1, 0, 0, 0); par_io_data_set(1, 29, 0); } of_node_put(np); } } #endif qe_fail: #endif /* CONFIG_QUICC_ENGINE */ printk(KERN_INFO "TWR-P1025 board from Freescale Semiconductor\n"); }
/* * Setup the architecture */ static void __init mpc85xx_rdb_setup_arch(void) { #ifdef CONFIG_QUICC_ENGINE struct device_node *np; #endif #if defined(CONFIG_QUICC_ENGINE) && defined(CONFIG_SPI_FSL_SPI) struct device_node *qe_spi; #endif struct ccsr_guts __iomem *guts; if (ppc_md.progress) ppc_md.progress("mpc85xx_rdb_setup_arch()", 0); mpc85xx_smp_init(); fsl_pci_assign_primary(); #ifdef CONFIG_QUICC_ENGINE np = of_find_compatible_node(NULL, NULL, "fsl,qe"); if (!np) { pr_err("%s: Could not find Quicc Engine node\n", __func__); goto qe_fail; } qe_reset(); of_node_put(np); np = of_find_node_by_name(NULL, "par_io"); if (np) { struct device_node *ucc; par_io_init(np); of_node_put(np); for_each_node_by_name(ucc, "ucc") par_io_of_config(ucc); /* To P1025 QE/TDM, the name of ucc nodes is "tdm@xxxx" */ for_each_node_by_name(ucc, "tdm") par_io_of_config(ucc); #ifdef CONFIG_SPI_FSL_SPI for_each_node_by_name(qe_spi, "spi") par_io_of_config(qe_spi); #endif /* CONFIG_SPI_FSL_SPI */ } np = of_find_node_by_name(NULL, "global-utilities"); if (np) { guts = of_iomap(np, 0); if (!guts) pr_err("mpc85xx-rdb: could not map global " "utilities register\n"); else { #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) if (machine_is(p1025_rdb)) { /* * P1025 has pins muxed for QE and other * functions. To enable QE UEC mode, we * need to set bit QE0 for UCC1 in Eth mode, * QE0 and QE3 for UCC5 in Eth mode, QE9 * and QE12 for QE MII management singals * in PMUXCR register. */ setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | MPC85xx_PMUXCR_QE(3) | MPC85xx_PMUXCR_QE(9) | MPC85xx_PMUXCR_QE(12)); } #endif #ifdef CONFIG_FSL_UCC_TDM if (machine_is(p1021_rdb_pc) || machine_is(p1025_rdb)) { /* Clear QE12 for releasing the LBCTL */ clrbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(12)); /* TDMA */ setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(5) | MPC85xx_PMUXCR_QE(11)); /* TDMB */ setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | MPC85xx_PMUXCR_QE(9)); /* TDMC */ setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0)); /* TDMD */ setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(8) | MPC85xx_PMUXCR_QE(7)); } #endif /* CONFIG_FSL_UCC_TDM */ #ifdef CONFIG_SPI_FSL_SPI if (of_find_compatible_node(NULL, NULL, "fsl,mpc8569-qe-spi")) { clrbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(12)); /*QE-SPI*/ setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(6) | MPC85xx_PMUXCR_QE(9) | MPC85xx_PMUXCR_QE(10)); } #endif /* CONFIG_SPI_FSL_SPI */ iounmap(guts); } of_node_put(np); } qe_fail: #endif /* CONFIG_QUICC_ENGINE */ printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n"); }
/* ************************************************************************ * * Setup the architecture * */ static void __init mpc83xx_km_setup_arch(void) { struct device_node *np; if (ppc_md.progress) ppc_md.progress("kmpbec83xx_setup_arch()", 0); #ifdef CONFIG_PCI for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") mpc83xx_add_bridge(np); #endif #ifdef CONFIG_QUICC_ENGINE qe_reset(); np = of_find_node_by_name(NULL, "par_io"); if (np != NULL) { par_io_init(np); of_node_put(np); for_each_node_by_name(np, "spi") par_io_of_config(np); for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;) par_io_of_config(np); } np = of_find_compatible_node(NULL, "network", "ucc_geth"); if (np != NULL) { uint svid; /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */ svid = mfspr(SPRN_SVR); if (SVR_REV(svid) == 0x0021) { struct device_node *np_par; struct resource res; void __iomem *base; int ret; np_par = of_find_node_by_name(NULL, "par_io"); if (np_par == NULL) { printk(KERN_WARNING "%s couldn;t find par_io node\n", __func__); return; } /* Map Parallel I/O ports registers */ ret = of_address_to_resource(np_par, 0, &res); if (ret) { printk(KERN_WARNING "%s couldn;t map par_io registers\n", __func__); return; } base = ioremap(res.start, resource_size(&res)); /* * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) */ setbits32((base + 0xa8), 0x0c003000); /* * IMMR + 0x14AC[20:27] = 10101010 * (data delay for both UCC's) */ clrsetbits_be32((base + 0xac), 0xff0, 0xaa0); iounmap(base); of_node_put(np_par); } of_node_put(np); } #endif /* CONFIG_QUICC_ENGINE */ }