void gendsrlv(void)
{
#ifdef INTERPRET_DSRLV
gencallinterp((unsigned int)cached_interpreter_table.DSRLV, 0);
#else
int rt1, rt2, rd1, rd2;
allocate_register_manually(ECX, (unsigned int *)dst->f.r.rs);
rt1 = allocate_64_register1((unsigned int *)dst->f.r.rt);
rt2 = allocate_64_register2((unsigned int *)dst->f.r.rt);
rd1 = allocate_64_register1_w((unsigned int *)dst->f.r.rd);
rd2 = allocate_64_register2_w((unsigned int *)dst->f.r.rd);
if (rd1 != ECX && rd2 != ECX)
{
mov_reg32_reg32(rd1, rt1);
mov_reg32_reg32(rd2, rt2);
shrd_reg32_reg32_cl(rd1,rd2);
shr_reg32_cl(rd2);
test_reg32_imm32(ECX, 0x20);
je_rj(4);
mov_reg32_reg32(rd1, rd2); // 2
xor_reg32_reg32(rd2, rd2); // 2
}
else
{
int temp1, temp2;
force_32(ECX);
temp1 = lru_register();
temp2 = lru_register_exc1(temp1);
free_register(temp1);
free_register(temp2);
mov_reg32_reg32(temp1, rt1);
mov_reg32_reg32(temp2, rt2);
shrd_reg32_reg32_cl(temp1, temp2);
shr_reg32_cl(temp2);
test_reg32_imm32(ECX, 0x20);
je_rj(4);
mov_reg32_reg32(temp1, temp2); // 2
xor_reg32_reg32(temp2, temp2); // 2
mov_reg32_reg32(rd1, temp1);
mov_reg32_reg32(rd2, temp2);
}
#endif
}
void gendsrav()
{
#ifdef INTERPRET_DSRAV
gencallinterp((unsigned long)DSRAV, 0);
#else
int rt1, rt2, rd1, rd2;
allocate_register_manually(ECX, (unsigned long *)dst->f.r.rs);
rt1 = allocate_64_register1((unsigned long *)dst->f.r.rt);
rt2 = allocate_64_register2((unsigned long *)dst->f.r.rt);
rd1 = allocate_64_register1_w((unsigned long *)dst->f.r.rd);
rd2 = allocate_64_register2_w((unsigned long *)dst->f.r.rd);
if (rd1 != ECX && rd2 != ECX)
{
mov_reg32_reg32(rd1, rt1);
mov_reg32_reg32(rd2, rt2);
shrd_reg32_reg32_cl(rd1,rd2);
sar_reg32_cl(rd2);
test_reg32_imm32(ECX, 0x20);
je_rj(5);
mov_reg32_reg32(rd1, rd2); // 2
sar_reg32_imm8(rd2, 31); // 3
}
else
{
int temp1, temp2;
force_32(ECX);
temp1 = lru_register();
temp2 = lru_register_exc1(temp1);
free_register(temp1);
free_register(temp2);
mov_reg32_reg32(temp1, rt1);
mov_reg32_reg32(temp2, rt2);
shrd_reg32_reg32_cl(temp1, temp2);
sar_reg32_cl(temp2);
test_reg32_imm32(ECX, 0x20);
je_rj(5);
mov_reg32_reg32(temp1, temp2); // 2
sar_reg32_imm8(temp2, 31); // 3
mov_reg32_reg32(rd1, temp1);
mov_reg32_reg32(rd2, temp2);
}
#endif
}
void gendsrav(usf_state_t * state)
{
#ifdef INTERPRET_DSRAV
gencallinterp(state, (unsigned int)state->current_instruction_table.DSRAV, 0);
#else
int rt1, rt2, rd1, rd2;
allocate_register_manually(state, ECX, (unsigned int *)state->dst->f.r.rs);
rt1 = allocate_64_register1(state, (unsigned int *)state->dst->f.r.rt);
rt2 = allocate_64_register2(state, (unsigned int *)state->dst->f.r.rt);
rd1 = allocate_64_register1_w(state, (unsigned int *)state->dst->f.r.rd);
rd2 = allocate_64_register2_w(state, (unsigned int *)state->dst->f.r.rd);
if (rd1 != ECX && rd2 != ECX)
{
mov_reg32_reg32(state, rd1, rt1);
mov_reg32_reg32(state, rd2, rt2);
shrd_reg32_reg32_cl(state, rd1,rd2);
sar_reg32_cl(state, rd2);
test_reg32_imm32(state, ECX, 0x20);
je_rj(state, 5);
mov_reg32_reg32(state, rd1, rd2); // 2
sar_reg32_imm8(state, rd2, 31); // 3
}
else
{
int temp1, temp2;
force_32(state, ECX);
temp1 = lru_register(state);
temp2 = lru_register_exc1(state, temp1);
free_register(state, temp1);
free_register(state, temp2);
mov_reg32_reg32(state, temp1, rt1);
mov_reg32_reg32(state, temp2, rt2);
shrd_reg32_reg32_cl(state, temp1, temp2);
sar_reg32_cl(state, temp2);
test_reg32_imm32(state, ECX, 0x20);
je_rj(state, 5);
mov_reg32_reg32(state, temp1, temp2); // 2
sar_reg32_imm8(state, temp2, 31); // 3
mov_reg32_reg32(state, rd1, temp1);
mov_reg32_reg32(state, rd2, temp2);
}
#endif
}