static int fpga_reset (fpga_t* fpga)
{
int i;
/* Set PROG to low and wait til INIT goes low */
fpga_control(fpga, FPGA_PROG_SET_LOW);
for (i = 0; i < FPGA_RESET_TIMEOUT; i++) {
udelay (100);
if (!fpga_control(fpga, FPGA_INIT_IS_HIGH))
break;
}
if (i == FPGA_RESET_TIMEOUT)
goto failure;
/* Set PROG to high and wait til INIT goes high */
fpga_control(fpga, FPGA_PROG_SET_HIGH);
for (i = 0; i < FPGA_RESET_TIMEOUT; i++) {
udelay (100);
if (fpga_control(fpga, FPGA_INIT_IS_HIGH))
break;
}
if (i == FPGA_RESET_TIMEOUT)
goto failure;
return 0;
failure:
return 1;
}
int fpga_init (void)
{
ulong addr;
ulong new_id, old_id = 0;
image_header_t *hdr;
fpga_t* fpga;
int do_load, i, j;
char name[16], *s;
/*
* Port setup for FPGA control
*/
for (i = 0; i < fpga_count; i++) {
fpga_control(&fpga_list[i], FPGA_INIT_PORTS);
}
/*
* Load FPGA(s): a new net-list is loaded if the FPGA is
* empty, Power-on-Reset or the old one is not up-to-date
*/
for (i = 0; i < fpga_count; i++) {
fpga = &fpga_list[i];
printf ("%s: ", fpga->name);
for (j = 0; j < strlen(fpga->name); j++)
name[j] = tolower(fpga->name[j]);
name[j] = '\0';
sprintf(name, "%s_addr", name);
addr = 0;
if ((s = getenv(name)) != NULL)
addr = simple_strtoul(s, NULL, 16);
if (!addr) {
printf ("env. variable %s undefined\n", name);
return 1;
}
hdr = (image_header_t *)addr;
if ((new_id = fpga_get_version(fpga, hdr->ih_name)) == -1)
return 1;
do_load = 1;
if (!power_on_reset() && fpga_control(fpga, FPGA_DONE_IS_HIGH)) {
old_id = fpga_control(fpga, FPGA_GET_ID);
if (new_id == old_id)
do_load = 0;
}
if (do_load) {
printf ("loading ");
fpga_load (fpga, addr, 0);
} else {
printf ("loaded (%08lx)\n", old_id);
}
}
return 0;
}
static void fpga_status (fpga_t* fpga)
{
/* Check state */
if (fpga_control(fpga, FPGA_DONE_IS_HIGH))
printf ("%s is loaded (%08lx)\n",
fpga->name, fpga_control(fpga, FPGA_GET_ID));
else
printf ("%s is NOT loaded\n", fpga->name);
}
static int fpga_load (fpga_t* fpga, ulong addr, int checkall)
{
volatile uchar *fpga_addr = (volatile uchar *)fpga->conf_base;
image_header_t hdr;
ulong len, checksum;
uchar *data = (uchar *)&hdr;
char *s, msg[32];
int verify, i;
/*
* Check the image header and data of the net-list
*/
memcpy (&hdr, (char *)addr, sizeof(image_header_t));
if (hdr.ih_magic != IH_MAGIC) {
strcpy (msg, "Bad Image Magic Number");
goto failure;
}
len = sizeof(image_header_t);
checksum = hdr.ih_hcrc;
hdr.ih_hcrc = 0;
if (crc32 (0, data, len) != checksum) {
strcpy (msg, "Bad Image Header CRC");
goto failure;
}
data = (uchar*)(addr + sizeof(image_header_t));
len = hdr.ih_size;
s = getenv ("verify");
verify = (s && (*s == 'n')) ? 0 : 1;
if (verify) {
if (crc32 (0, data, len) != hdr.ih_dcrc) {
strcpy (msg, "Bad Image Data CRC");
goto failure;
}
}
if (checkall && fpga_get_version(fpga, hdr.ih_name) < 0)
return 1;
/* align length */
if (len & 1)
++len;
/*
* Reset FPGA and wait for completion
*/
if (fpga_reset(fpga)) {
strcpy (msg, "Reset Timeout");
goto failure;
}
printf ("(%s)... ", hdr.ih_name);
/*
* Copy data to FPGA
*/
fpga_control (fpga, FPGA_LOAD_MODE);
while (len--) {
*fpga_addr = *data++;
}
fpga_control (fpga, FPGA_READ_MODE);
/*
* Wait for completion and check error status if timeout
*/
for (i = 0; i < FPGA_LOAD_TIMEOUT; i++) {
udelay (100);
if (fpga_control (fpga, FPGA_DONE_IS_HIGH))
break;
}
if (i == FPGA_LOAD_TIMEOUT) {
if (fpga_control(fpga, FPGA_INIT_IS_HIGH))
strcpy(msg, "Invalid Size");
else
strcpy(msg, "CRC Error");
goto failure;
}
printf("done\n");
return 0;
failure:
printf("ERROR: %s\n", msg);
return 1;
}
static int fpga_load (fpga_t* fpga, ulong addr, int checkall)
{
volatile uchar *fpga_addr = (volatile uchar *)fpga->conf_base;
image_header_t *hdr = (image_header_t *)addr;
ulong len;
uchar *data;
char msg[32];
int verify, i;
#if defined(CONFIG_FIT)
if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
puts ("Non legacy image format not supported\n");
return -1;
}
#endif
/*
* Check the image header and data of the net-list
*/
if (!image_check_magic (hdr)) {
strcpy (msg, "Bad Image Magic Number");
goto failure;
}
if (!image_check_hcrc (hdr)) {
strcpy (msg, "Bad Image Header CRC");
goto failure;
}
data = (uchar*)image_get_data (hdr);
len = image_get_data_size (hdr);
verify = getenv_yesno ("verify");
if (verify) {
if (!image_check_dcrc (hdr)) {
strcpy (msg, "Bad Image Data CRC");
goto failure;
}
}
if (checkall && fpga_get_version(fpga, image_get_name (hdr)) < 0)
return 1;
/* align length */
if (len & 1)
++len;
/*
* Reset FPGA and wait for completion
*/
if (fpga_reset(fpga)) {
strcpy (msg, "Reset Timeout");
goto failure;
}
printf ("(%s)... ", image_get_name (hdr));
/*
* Copy data to FPGA
*/
fpga_control (fpga, FPGA_LOAD_MODE);
while (len--) {
*fpga_addr = *data++;
}
fpga_control (fpga, FPGA_READ_MODE);
/*
* Wait for completion and check error status if timeout
*/
for (i = 0; i < FPGA_LOAD_TIMEOUT; i++) {
udelay (100);
if (fpga_control (fpga, FPGA_DONE_IS_HIGH))
break;
}
if (i == FPGA_LOAD_TIMEOUT) {
if (fpga_control(fpga, FPGA_INIT_IS_HIGH))
strcpy(msg, "Invalid Size");
else
strcpy(msg, "CRC Error");
goto failure;
}
printf("done\n");
return 0;
failure:
printf("ERROR: %s\n", msg);
return 1;
}
