/* * Slow path interrupt handler for FPGAs. */ static int fpga_slow_intr(adapter_t *adapter) { u32 cause = readl(adapter->regs + A_PL_CAUSE); cause &= ~F_PL_INTR_SGE_DATA; if (cause & F_PL_INTR_SGE_ERR) t1_sge_intr_error_handler(adapter->sge); if (cause & FPGA_PCIX_INTERRUPT_GMAC) fpga_phy_intr_handler(adapter); if (cause & FPGA_PCIX_INTERRUPT_TP) { /* * FPGA doesn't support MC4 interrupts and it requires * this odd layer of indirection for MC5. */ u32 tp_cause = readl(adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE); /* Clear TP interrupt */ writel(tp_cause, adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE); } if (cause & FPGA_PCIX_INTERRUPT_PCIX) t1_pci_intr_handler(adapter); /* Clear the interrupts just processed. */ if (cause) writel(cause, adapter->regs + A_PL_CAUSE); return cause != 0; }
static int fpga_slow_intr(adapter_t *adapter) { u32 cause = readl(adapter->regs + A_PL_CAUSE); cause &= ~F_PL_INTR_SGE_DATA; if (cause & F_PL_INTR_SGE_ERR) t1_sge_intr_error_handler(adapter->sge); if (cause & FPGA_PCIX_INTERRUPT_GMAC) fpga_phy_intr_handler(adapter); if (cause & FPGA_PCIX_INTERRUPT_TP) { u32 tp_cause = readl(adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE); writel(tp_cause, adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE); } if (cause & FPGA_PCIX_INTERRUPT_PCIX) t1_pci_intr_handler(adapter); if (cause) writel(cause, adapter->regs + A_PL_CAUSE); return cause != 0; }