static void __init mpc85xx_ads_setup_arch(void) { struct device_node *cpu; #ifdef CONFIG_PCI struct device_node *np; #endif if (ppc_md.progress) ppc_md.progress("mpc85xx_ads_setup_arch()", 0); cpu = of_find_node_by_type(NULL, "cpu"); if (cpu != 0) { const unsigned int *fp; fp = of_get_property(cpu, "clock-frequency", NULL); if (fp != 0) loops_per_jiffy = *fp / HZ; else loops_per_jiffy = 50000000 / HZ; of_node_put(cpu); } #ifdef CONFIG_CPM2 cpm2_reset(); #endif #ifdef CONFIG_PCI for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) fsl_add_bridge(np, 1); ppc_md.pci_exclude_device = mpc85xx_exclude_device; #endif }
/* * Setup the architecture */ static void __init socrates_setup_arch(void) { #ifdef CONFIG_PCI struct device_node *np; #endif if (ppc_md.progress) ppc_md.progress("socrates_setup_arch()", 0); #ifdef CONFIG_PCI for_each_compatible_node(np, "pci", "fsl,mpc8540-pci") fsl_add_bridge(np, 1); #endif }
/* * Setup the architecture */ static void __init mpc8544_ds_setup_arch(void) { #ifdef CONFIG_PCI struct device_node *np; #endif if (ppc_md.progress) ppc_md.progress("mpc8544_ds_setup_arch()", 0); #ifdef CONFIG_PCI for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) { struct resource rsrc; of_address_to_resource(np, 0, &rsrc); if ((rsrc.start & 0xfffff) == 0xb000) fsl_add_bridge(np, 1); else fsl_add_bridge(np, 0); } uses_fsl_uli_m1575 = 1; ppc_md.pci_exclude_device = mpc85xx_exclude_device; #endif printk("MPC8544 DS board from Freescale Semiconductor\n"); }
static void __init mpc85xx_rds_setup_arch(void) { struct device_node *np; if (ppc_md.progress) ppc_md.progress("p1023_rds_setup_arch()", 0); /* */ np = of_find_node_by_name(NULL, "bcsr"); if (np != NULL) { static u8 __iomem *bcsr_regs; bcsr_regs = of_iomap(np, 0); of_node_put(np); if (!bcsr_regs) { printk(KERN_ERR "BCSR: Failed to map bcsr register space\n"); return; } else { #define BCSR15_I2C_BUS0_SEG_CLR 0x07 #define BCSR15_I2C_BUS0_SEG2 0x02 /* */ #ifdef CONFIG_RTC_CLASS /* */ clrbits8(&bcsr_regs[15], BCSR15_I2C_BUS0_SEG_CLR); setbits8(&bcsr_regs[15], BCSR15_I2C_BUS0_SEG2); #endif iounmap(bcsr_regs); } } #ifdef CONFIG_PCI for_each_compatible_node(np, "pci", "fsl,p1023-pcie") fsl_add_bridge(np, 0); #endif mpc85xx_smp_init(); }
/* ************************************************************************ * * Setup the architecture * */ static void __init mpc85xx_rds_setup_arch(void) { struct device_node *np; if (ppc_md.progress) ppc_md.progress("p1023_rds_setup_arch()", 0); /* Map BCSR area */ np = of_find_node_by_name(NULL, "bcsr"); if (np != NULL) { static u8 __iomem *bcsr_regs; bcsr_regs = of_iomap(np, 0); of_node_put(np); if (!bcsr_regs) { printk(KERN_ERR "BCSR: Failed to map bcsr register space\n"); return; } else { #define BCSR15_I2C_BUS0_SEG_CLR 0x07 #define BCSR15_I2C_BUS0_SEG2 0x02 /* * Note: Accessing exclusively i2c devices. * * The i2c controller selects initially ID EEPROM in the u-boot; * but if menu configuration selects RTC support in the kernel, * the i2c controller switches to select RTC chip in the kernel. */ #ifdef CONFIG_RTC_CLASS /* Enable RTC chip on the segment #2 of i2c */ clrbits8(&bcsr_regs[15], BCSR15_I2C_BUS0_SEG_CLR); setbits8(&bcsr_regs[15], BCSR15_I2C_BUS0_SEG2); #endif iounmap(bcsr_regs); } } #ifdef CONFIG_PCI for_each_compatible_node(np, "pci", "fsl,p1023-pcie") fsl_add_bridge(np, 0); #endif mpc85xx_smp_init(); }
static void __init sbc8560_setup_arch(void) { #ifdef CONFIG_PCI struct device_node *np; #endif if (ppc_md.progress) ppc_md.progress("sbc8560_setup_arch()", 0); #ifdef CONFIG_CPM2 cpm2_reset(); init_ioports(); #endif #ifdef CONFIG_PCI for_each_compatible_node(np, "pci", "fsl,mpc8540-pci") fsl_add_bridge(np, 1); #endif }
static void __init sbc8641_setup_arch(void) { #ifdef CONFIG_PCI struct device_node *np; #endif if (ppc_md.progress) ppc_md.progress("sbc8641_setup_arch()", 0); #ifdef CONFIG_PCI for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie") fsl_add_bridge(np, 0); #endif printk("SBC8641 board from Wind River\n"); #ifdef CONFIG_SMP mpc86xx_smp_init(); #endif }